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Date:   Tue, 28 Apr 2020 14:26:39 +0530
From:   Viresh Kumar <viresh.kumar@linaro.org>
To:     peng.fan@nxp.com
Cc:     shawnguo@kernel.org, s.hauer@pengutronix.de, rjw@rjwysocki.net,
        kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com,
        Anson.Huang@nxp.com, linux-pm@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH V2] cpufreq: imx-cpufreq-dt: support i.MX7ULP
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On 28-04-20, 15:21, peng.fan@nxp.com wrote:
> From: Peng Fan <peng.fan@nxp.com>
> 
> i.MX7ULP's ARM core clock design is totally different compared
> with i.MX7D/8M SoCs which supported by imx-cpufreq-dt. It needs
> get_intermediate and target_intermedate to configure clk MUX ready,
> before let OPP configure ARM core clk.
>                                           |---FIRC
>      |------RUN---...---SCS(MUX2) --------|
> ARM --(MUX1)                              |---SPLL_PFD0(CLK_SET_RATE_GATE)
>      |------HSRUN--...--HSRUN_SCS(MUX3)---|
>                                           |---SRIC
> 
> FIRC is step clk, SPLL_PFD0 is the normal clk driving ARM core.
> MUX2 and MUX3 share same inputs. So if MUX2/MUX3 both sources from
> SPLL_PFD0, both MUXes will lose input when configure SPLL_PFD0.
> So the target_intermediate will configure MUX2/MUX3 to FIRC, to avoid
> ARM core lose clk when configure SPLL_PFD0.
> 
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
> 
> V2:
>  Fix boot break. Tested on i.MX8MN DDR4 EVK.

Applied. Thanks.

-- 
viresh