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Wed, 29 Apr 2020 00:58:14 +0000 From: "Wan Mohamad, Wan Ahmad Zainie" To: Rob Herring CC: "kishon@ti.com" , "mark.rutland@arm.com" , "linux-kernel@vger.kernel.org" , "devicetree@vger.kernel.org" Subject: RE: [PATCH 1/2] dt-bindings: phy: intel: Add documentation for Keem Bay eMMC PHY Thread-Topic: [PATCH 1/2] dt-bindings: phy: intel: Add documentation for Keem Bay eMMC PHY Thread-Index: AQHV+38Ct5ErQ2mOFESCzgducVHEHqhhqx6AgC3fF6A= Date: Wed, 29 Apr 2020 00:58:14 +0000 Message-ID: References: <20200316103726.16339-1-wan.ahmad.zainie.wan.mohamad@intel.com> <20200316103726.16339-2-wan.ahmad.zainie.wan.mohamad@intel.com> <20200330202321.GA9386@bogus> In-Reply-To: <20200330202321.GA9386@bogus> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-reaction: no-action dlp-version: 11.2.0.6 authentication-results: kernel.org; dkim=none (message not signed) header.d=none;kernel.org; dmarc=none action=none header.from=intel.com; x-originating-ip: [192.198.147.221] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 5793077f-b375-4bb8-baa8-08d7ebd865a2 x-ms-traffictypediagnostic: DM6PR11MB3610: x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:2043; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 5793077f-b375-4bb8-baa8-08d7ebd865a2 X-MS-Exchange-CrossTenant-originalarrivaltime: 29 Apr 2020 00:58:14.5611 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: zGl7A8s/IIDTfpBbGn7enRarEbPn327pEHhIu0ttuzZdF914QKKsEF/CI/moxdLn3k5ZaIGePQ8wgdLvRlwfi9/Ek52LqL/64azmbC2JRgr4ghbhGf/kWfiC5WZx9a0o X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR11MB3610 X-OriginatorOrg: intel.com Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > -----Original Message----- > From: Rob Herring > Sent: Tuesday, March 31, 2020 4:23 AM > To: Wan Mohamad, Wan Ahmad Zainie > > Cc: kishon@ti.com; mark.rutland@arm.com; linux-kernel@vger.kernel.org; > devicetree@vger.kernel.org > Subject: Re: [PATCH 1/2] dt-bindings: phy: intel: Add documentation for > Keem Bay eMMC PHY >=20 > On Mon, Mar 16, 2020 at 06:37:25PM +0800, Wan Ahmad Zainie wrote: > > Document Intel Keem Bay eMMC PHY DT bindings. > > > > Signed-off-by: Wan Ahmad Zainie > > > --- > > .../bindings/phy/intel,keembay-emmc-phy.yaml | 57 > +++++++++++++++++++ > > 1 file changed, 57 insertions(+) > > create mode 100644 > Documentation/devicetree/bindings/phy/intel,keembay-emmc-phy.yaml > > > > diff --git a/Documentation/devicetree/bindings/phy/intel,keembay- > emmc-phy.yaml b/Documentation/devicetree/bindings/phy/intel,keembay- > emmc-phy.yaml > > new file mode 100644 > > index 000000000000..af1d62fc8323 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/phy/intel,keembay-emmc- > phy.yaml > > @@ -0,0 +1,57 @@ > > +# SPDX-License-Identifier: GPL-2.0-only >=20 > Dual license new bindings: >=20 > (GPL-2.0-only OR BSD-2-Clause) Will change in v2. >=20 > > +# Copyright 2020 Intel Corporation > > +%YAML 1.2 > > +--- > > +$id: "http://devicetree.org/schemas/phy/intel,keembay-emmc- > phy.yaml#" > > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" > > + > > +title: Intel Keem Bay eMMC PHY > > + > > +maintainers: > > + - Wan Ahmad Zainie > > + > > +properties: > > + compatible: > > + enum: > > + - intel,keembay-emmc-phy > > + > > + reg: > > + maxItems: 1 > > + > > + clocks: > > + maxItems: 1 > > + > > + clock-names: > > + items: > > + - const: emmcclk > > + > > + intel,syscon: > > + $ref: '/schemas/types.yaml#/definitions/phandle' >=20 > Make this binding a child of the syscon and get rid of this. >=20 > > + description: > > + A phandle to a syscon device used to access core/phy configurati= on > > + registers. > > + > > + "#phy-cells": > > + const: 0 > > + > > +required: > > + - compatible > > + - reg > > + - intel,syscon > > + - "#phy-cells" > > + > > +examples: > > + - | > > + mmc_phy_syscon: syscon@20290000 { > > + compatible =3D "simple-mfd", "syscon"; > > + reg =3D <0x0 0x20290000 0x0 0x54>; > > + }; > > + > > + emmc_phy: mmc_phy@20290000 { >=20 > phy@... Will change in v2. >=20 > > + compatible =3D "intel,keembay-emmc-phy"; > > + reg =3D <0x0 0x20290000 0x0 0x54>; >=20 > Here you have overlapping register regions. Don't do that. >=20 > Given they are the same size, why do you need the syscon at all? In v2, the driver will use regmap_mmio. With that, can remove intel,syscon. I will send out once reviewed internally. >=20 > > + clocks =3D <&mmc>; > > + clock-names =3D "emmcclk"; > > + intel,syscon =3D <&mmc_phy_syscon>; > > + #phy-cells =3D <0>; > > + }; > > -- > > 2.17.1 > >