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Date:   Wed, 29 Apr 2020 12:06:25 +1000
From:   Stephen Rothwell <sfr@canb.auug.org.au>
To:     Leon Romanovsky <leon@kernel.org>,
        "Gustavo A. R. Silva" <gustavo@embeddedor.com>
Cc:     Linux Next Mailing List <linux-next@vger.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        Huy Nguyen <huyn@mellanox.com>,
        Saeed Mahameed <saeedm@mellanox.com>,
        Raed Salem <raeds@mellanox.com>
Subject: linux-next: manual merge of the mlx5-next tree with the
 kspp-gustavo tree
Message-ID: <20200429120625.2b5bb507@canb.auug.org.au>
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Hi all,

Today's linux-next merge of the mlx5-next tree got a conflict in:

  include/linux/mlx5/mlx5_ifc.h

between commit:

  3ba225b506a2 ("treewide: Replace zero-length array with flexible-array me=
mber")

from the kspp-gustavo tree and commit:

  d65dbedfd298 ("net/mlx5: Add support for COPY steering action")

from the mlx5-next tree.

I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging.  You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.

--=20
Cheers,
Stephen Rothwell

diff --cc include/linux/mlx5/mlx5_ifc.h
index 8d30f18dcdee,fb243848132d..000000000000
--- a/include/linux/mlx5/mlx5_ifc.h
+++ b/include/linux/mlx5/mlx5_ifc.h
@@@ -5743,7 -5771,7 +5771,7 @@@ struct mlx5_ifc_alloc_modify_header_con
  	u8         reserved_at_68[0x10];
  	u8         num_of_actions[0x8];
 =20
- 	union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[];
 -	union mlx5_ifc_set_add_copy_action_in_auto_bits actions[0];
++	union mlx5_ifc_set_add_copy_action_in_auto_bits actions[];
  };
 =20
  struct mlx5_ifc_dealloc_modify_header_context_out_bits {
@@@ -9677,9 -9705,32 +9705,32 @@@ struct mlx5_ifc_mcda_reg_bits=20
 =20
  	u8         reserved_at_60[0x20];
 =20
 -	u8         data[0][0x20];
 +	u8         data[][0x20];
  };
 =20
+ enum {
+ 	MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP =3D BIT(0),
+ 	MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE =3D BIT(1),
+ };
+=20
+ enum {
+ 	MLX5_MFRL_REG_RESET_LEVEL0 =3D BIT(0),
+ 	MLX5_MFRL_REG_RESET_LEVEL3 =3D BIT(3),
+ 	MLX5_MFRL_REG_RESET_LEVEL6 =3D BIT(6),
+ };
+=20
+ struct mlx5_ifc_mfrl_reg_bits {
+ 	u8         reserved_at_0[0x20];
+=20
+ 	u8         reserved_at_20[0x2];
+ 	u8         pci_sync_for_fw_update_start[0x1];
+ 	u8         pci_sync_for_fw_update_resp[0x2];
+ 	u8         rst_type_sel[0x3];
+ 	u8         reserved_at_28[0x8];
+ 	u8         reset_type[0x8];
+ 	u8         reset_level[0x8];
+ };
+=20
  struct mlx5_ifc_mirc_reg_bits {
  	u8         reserved_at_0[0x18];
  	u8         status_code[0x8];

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