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Subject: Re: [PATCH 1/4] spi: lantiq: Synchronize interrupt handlers and
 transfers
To:     Hauke Mehrtens <hauke@hauke-m.de>,
        Daniel Schwierzeck <daniel.schwierzeck@gmail.com>,
        broonie@kernel.org, robh@kernel.org, linux-spi@vger.kernel.org,
        devicetree@vger.kernel.org
Cc:     linux-kernel@vger.kernel.org, andriy.shevchenko@intel.com,
        cheol.yong.kim@intel.com, chuanhua.lei@linux.intel.com,
        qi-ming.wu@intel.com
References: <cover.1587702428.git.eswara.kota@linux.intel.com>
 <3bf88d24b9cad9f3df1da8ed65bf55c05693b0f2.1587702428.git.eswara.kota@linux.intel.com>
 <310ca761-e7ae-1192-99fd-a1960697806b@gmail.com>
 <262f2739-494a-a59b-f1e9-80a95ea465b1@hauke-m.de>
From:   Dilip Kota <eswara.kota@linux.intel.com>
Message-ID: <078a68ad-b82b-81c5-2d93-bfa4b70bc5d6@linux.intel.com>
Date:   Wed, 29 Apr 2020 16:22:33 +0800
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On 4/28/2020 7:30 PM, Hauke Mehrtens wrote:
> On 4/28/20 1:10 PM, Daniel Schwierzeck wrote:
>>
>> Am 24.04.20 um 12:42 schrieb Dilip Kota:
>>
...
> Hi,
>
> The Interrupt controller found on Danube till xrx300 which is probably
> from Infineon like this SPI controller IP acknowledges the interrupts
> also inside this SPI controller IP automatically, this has to be done
> manually on the xrx500 and probably also LGM as they use a different
> interrupt controller. I prepared patches for this internally 2.5 years
> ago but did not send them upstream because of internal processes.
>
> I would suggest to only do this ack on the newer platforms starting with
> the xrx500 and not on the older.
>
> On SMP systems a lock is needed in lantiq_ssc_xmit_interrupt() to
> protect against an other thread reading from the RX buffer or writing to
> the TX buffer in parallel.
>
> @Dilip. Did you try the patches I send you one months ago on the LGM?
All the cases you mentioned are taken care in the patch, could you 
please have a look once.

And the patch you shared internally, has done below change. By referring 
it i have updated the offsets, mentioning offsets are wrong. But actual 
case is vrx200 are having different offsets and xrx500, latest chipsets 
are having different offsets. I think this could be the reason for SPI 
transfer timeouts when you run test on vrx200 with my patches.

-#define LTQ_SPI_IRNICR		0xf8
-#define LTQ_SPI_IRNCR		0xfc
+#define LTQ_SPI_IRNCR		0xf8
+#define LTQ_SPI_IRNICR		0xfc

These offsets need to be defined in SoC data structure as they are 
different across the chipsets(which i have done in initial phase of the 
patch which i submitted for internal review. I hope you had got a chance 
to review it).

Regards,
Dilip