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Wed, 29 Apr 2020 15:27:58 +0000 Subject: Re: [PATCH v29 00/20] Intel SGX foundations To: Jarkko Sakkinen , linux-kernel@vger.kernel.org, x86@kernel.org, linux-sgx@vger.kernel.org Cc: akpm@linux-foundation.org, dave.hansen@intel.com, sean.j.christopherson@intel.com, nhorman@redhat.com, npmccallum@redhat.com, haitao.huang@intel.com, andriy.shevchenko@linux.intel.com, tglx@linutronix.de, kai.svahn@intel.com, bp@alien8.de, josh@joshtriplett.org, luto@kernel.org, kai.huang@intel.com, rientjes@google.com, cedric.xing@intel.com, puiterwijk@redhat.com References: <20200421215316.56503-1-jarkko.sakkinen@linux.intel.com> From: Jethro Beekman Message-ID: <07c1a36c-cebc-3a65-6f92-4a5498fcc369@fortanix.com> Date: Wed, 29 Apr 2020 17:27:48 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.7.0 In-Reply-To: <20200421215316.56503-1-jarkko.sakkinen@linux.intel.com> Content-Type: multipart/signed; protocol="application/pkcs7-signature"; micalg=sha-256; boundary="------------ms000605070402020109060108" X-ClientProxiedBy: AM0PR01CA0094.eurprd01.prod.exchangelabs.com (2603:10a6:208:10e::35) To BY5PR11MB4260.namprd11.prod.outlook.com (2603:10b6:a03:1ba::30) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from [192.168.4.219] (213.127.61.179) by AM0PR01CA0094.eurprd01.prod.exchangelabs.com (2603:10a6:208:10e::35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2958.20 via Frontend Transport; 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charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: quoted-printable On 2020-04-21 23:52, Jarkko Sakkinen wrote: > Intel(R) SGX is a set of CPU instructions that can be used by applicati= ons > to set aside private regions of code and data. The code outside the enc= lave > is disallowed to access the memory inside the enclave by the CPU access= > control. >=20 > There is a new hardware unit in the processor called Memory Encryption > Engine (MEE) starting from the Skylake microacrhitecture. BIOS can defi= ne > one or many MEE regions that can hold enclave data by configuring them = with > PRMRR registers. >=20 > The MEE automatically encrypts the data leaving the processor package t= o > the MEE regions. The data is encrypted using a random key whose life-ti= me > is exactly one power cycle. >=20 > The current implementation requires that the firmware sets > IA32_SGXLEPUBKEYHASH* MSRs as writable so that ultimately the kernel ca= n > decide what enclaves it wants run. The implementation does not create > any bottlenecks to support read-only MSRs later on. >=20 > You can tell if your CPU supports SGX by looking into /proc/cpuinfo: >=20 > cat /proc/cpuinfo | grep sgx Let's merge this. -- Jethro Beekman | Fortanix --------------ms000605070402020109060108 Content-Type: application/pkcs7-signature; name="smime.p7s" Content-Transfer-Encoding: base64 Content-Disposition: attachment; filename="smime.p7s" Content-Description: S/MIME Cryptographic Signature MIAGCSqGSIb3DQEHAqCAMIACAQExDzANBglghkgBZQMEAgEFADCABgkqhkiG9w0BBwEAAKCC C54wggVPMIIEN6ADAgECAhAFFr+cC0ZYZTtbKgQCBwyyMA0GCSqGSIb3DQEBCwUAMIGCMQsw CQYDVQQGEwJJVDEPMA0GA1UECAwGTWlsYW5vMQ8wDQYDVQQHDAZNaWxhbm8xIzAhBgNVBAoM GkFjdGFsaXMgUy5wLkEuLzAzMzU4NTIwOTY3MSwwKgYDVQQDDCNBY3RhbGlzIENsaWVudCBB dXRoZW50aWNhdGlvbiBDQSBHMTAeFw0xOTA5MTYwOTQ3MDlaFw0yMDA5MTYwOTQ3MDlaMB4x HDAaBgNVBAMME2pldGhyb0Bmb3J0YW5peC5jb20wggEiMA0GCSqGSIb3DQEBAQUAA4IBDwAw ggEKAoIBAQDHWEhcRGkEl1ZnImSqBt/OXNJ4AyDZ86CejuWI9jYpWbtf/gXBQO6iaaEKBDlj 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