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Subject: Re: [PATCH 2/2] x86/resctrl: Support CPUID enumeration of MBM counter
 width
To:     Borislav Petkov <bp@alien8.de>
Cc:     tglx@linutronix.de, fenghua.yu@intel.com, tony.luck@intel.com,
        kuo-lang.tseng@intel.com, mingo@redhat.com, babu.moger@amd.com,
        hpa@zytor.com, x86@kernel.org, linux-kernel@vger.kernel.org
References: <cover.1585763047.git.reinette.chatre@intel.com>
 <76dc65631c373e0c1c9f3e8aaa768f022a2c989c.1585763047.git.reinette.chatre@intel.com>
 <20200429181149.GE16407@zn.tnic>
From:   Reinette Chatre <reinette.chatre@intel.com>
Message-ID: <6fb58472-88f2-925b-3a4e-4692957a9582@intel.com>
Date:   Wed, 29 Apr 2020 11:42:03 -0700
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Hi Borislav,

On 4/29/2020 11:11 AM, Borislav Petkov wrote:
> On Wed, Apr 01, 2020 at 10:51:02AM -0700, Reinette Chatre wrote:
>> diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
>> index 4cdb123ff66a..8552d2fadc15 100644
>> --- a/arch/x86/kernel/cpu/common.c
>> +++ b/arch/x86/kernel/cpu/common.c
>> @@ -856,6 +856,8 @@ static void init_speculation_control(struct cpuinfo_x86 *c)
>>  
>>  static void init_cqm(struct cpuinfo_x86 *c)
>>  {
>> +	c->x86_cache_mbm_width_offset = -1;
>> +
>>  	if (!cpu_has(c, X86_FEATURE_CQM_LLC)) {
>>  		c->x86_cache_max_rmid  = -1;
>>  		c->x86_cache_occ_scale = -1;
>> @@ -875,6 +877,9 @@ static void init_cqm(struct cpuinfo_x86 *c)
>>  
>>  		c->x86_cache_max_rmid  = ecx;
>>  		c->x86_cache_occ_scale = ebx;
>> +		/* EAX contents is only defined for Intel CPUs */
>> +		if (c->x86_vendor == X86_VENDOR_INTEL)
>> +			c->x86_cache_mbm_width_offset = eax & 0xff;
> 
> Remind me again pls why is all this RDT stuff replicated per CPU instead
> of it being properly detected somewhere down in resctrl_late_init()?
> 
> Looking at get_rdt_resources(), it kinda wants to have that in there
> too?
> 
> IOW, how about moving all that gunk in init_cqm() to resctrl/ where it
> truly belongs? Doesn't have to be this patchset but this patchset can
> start moving it...

I am not familiar with the history to clarify to you why the RDT feature
enumeration is not consistent. Even so, there was an effort to
consolidate this in [1] but it was found to go against the goal of
centralizing the CPUID information [2] and was not pursued further. I
would be happy to revisit this if this is the direction that you prefer.
This would essentially be resubmitting [1] though. Do you expect that
this change would receive a different reception at this time?

Thank you

Reinette


[1]
https://lore.kernel.org/lkml/1560705250-211820-2-git-send-email-fenghua.yu@intel.com/

[2]
https://lore.kernel.org/lkml/alpine.DEB.2.21.1906162141301.1760@nanos.tec.linutronix.de/