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Date:   Wed, 29 Apr 2020 16:03:56 -0700
From:   Andi Kleen <ak@linux.intel.com>
To:     Adrian Hunter <adrian.hunter@intel.com>
Cc:     Arnaldo Carvalho de Melo <acme@kernel.org>,
        Jiri Olsa <jolsa@redhat.com>, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 8/9] perf intel-pt: Update documentation about itrace G
 and L options
Message-ID: <20200429230356.GB874567@tassilo.jf.intel.com>
References: <20200429150751.12570-1-adrian.hunter@intel.com>
 <20200429150751.12570-9-adrian.hunter@intel.com>
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> +One caveat with the G and L options is that they work poorly with "Large PEBS".
> +Large PEBS means PEBS records will be accumulated by hardware and the written
> +into the event buffer in one go.  That reduces interrupts, but can give very
> +late timestamps.  Because the Intel PT trace is synchronized by timestamps,

Are you refering to Broadwell here?

On Skylake/Goldmont the PEBS event contains the TSC and the time stamp reported by
perf should report the time the event was sampled based on that TSC. 
Or is that not working for some reason?

-Andi