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Date:   Thu, 30 Apr 2020 05:28:58 -0700
From:   Andi Kleen <ak@linux.intel.com>
To:     Adrian Hunter <adrian.hunter@intel.com>
Cc:     Arnaldo Carvalho de Melo <acme@kernel.org>,
        Jiri Olsa <jolsa@redhat.com>, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 8/9] perf intel-pt: Update documentation about itrace G
 and L options
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> > 
> > On Skylake/Goldmont the PEBS event contains the TSC and the time stamp reported by
> > perf should report the time the event was sampled based on that TSC. 
> > Or is that not working for some reason?
> 
> I guess it is not working like that, but perf tools would probably need
> special rules to sort the events because the they would break the rules of
> PERF_RECORD_FINISHED_ROUND, wouldn't they?

Yes it may violate finished round.

It should not be delayed longer than the next context switch though.

The documentation warning would be still correct, but only on Broadwell.

-Andi