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[209.85.221.179]) by smtp.gmail.com with ESMTPSA id y84sm897979vsc.14.2020.05.01.11.15.45 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 01 May 2020 11:15:45 -0700 (PDT) Received: by mail-vk1-f179.google.com with SMTP id v192so2899437vkd.3 for ; Fri, 01 May 2020 11:15:45 -0700 (PDT) X-Received: by 2002:a1f:5fc3:: with SMTP id t186mr3772515vkb.92.1588356945201; Fri, 01 May 2020 11:15:45 -0700 (PDT) MIME-Version: 1.0 References: <20200501161938.2949443-1-daniel.thompson@linaro.org> In-Reply-To: <20200501161938.2949443-1-daniel.thompson@linaro.org> From: Doug Anderson Date: Fri, 1 May 2020 11:15:33 -0700 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH] arm64: cacheflush: Fix KGDB trap detection To: Daniel Thompson Cc: Catalin Marinas , Will Deacon , Jason Wessel , Linux ARM , LKML , Patch Tracking Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On Fri, May 1, 2020 at 9:20 AM Daniel Thompson wrote: > > flush_icache_range() contains a bodge to avoid issuing IPIs when the kgdb > trap handler is running because issuing IPIs is unsafe (and unnecessary) > in this exection context. However the current test is flawed: it both s/exection/execution/ > over-matches (could skip the IPI when the kgdb trap is not running) and > under-matches (does not skip the IPI for all kgdb cache operations). Maybe explain why? I believe this is because "kgdb_connected" signifies that a host "gdb" is connected. * If we're sitting at the kdb prompt "kgdb_connected" won't be set but we might still try to do something with a breakpoint with interrupts off. * If we are currently _not_ stopped in the debugger but the host "gdb" is connected then "kgdb_connected" will continue to be set. In this context we will exit early if any other callers happen to try to cache flush with interrupts disabled. > Fix by replacing the ad-hoc check with the proper kgdb macro. This also > allows us to drop the #ifdef wrapper. > > Fixes: 3b8c9f1cdfc5 ("arm64: IPI each CPU after invalidating the I-cache for kernel mappings") > Signed-off-by: Daniel Thompson > --- > arch/arm64/include/asm/cacheflush.h | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) Other than the suggestions to the commit message: Reviewed-by: Douglas Anderson