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From:   Amit Sunil Dhamne <amit.sunil.dhamne@xilinx.com>
To:     mturquette@baylibre.com, sboyd@kernel.org, michal.simek@xilinx.com,
        mark.rutland@arm.com, linux-clk@vger.kernel.org
Cc:     rajanv@xilinx.com, jollys@xilinx.com,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,
        Tejas Patel <tejas.patel@xilinx.com>,
        Jolly Shah <jolly.shah@xilinx.com>,
        Amit Sunil Dhamne <amit.sunil.dhamne@xilinx.com>
Subject: [RESEND PATCH v2 2/4] drivers: clk: zynqmp: Fix divider2 calculation
Date:   Fri,  1 May 2020 21:37:01 -0700
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From: Tejas Patel <tejas.patel@xilinx.com>

zynqmp_get_divider2_val() calculates, divider value of type DIV2 clock,
considering best possible combination of DIV1 and DIV2.

To find best possible values of DIV1 and DIV2, DIV1's parent rate
should be consider and not DIV2's parent rate since it would rate of
div1 clock. Consider a below topology,

        out_clk->div2_clk->div1_clk->fixed_parent

where out_clk =3D (fixed_parent/div1_clk) / div2_clk, so parent clock
of div1_clk (i.e. out_clk) should be divided by div1_clk and div2_clk.

Existing code divides parent rate of div2_clk's clock instead of
div1_clk's parent rate, which is wrong.

Fix the same by considering div1's parent clock rate.

Fixes: 4ebd92d2e228 ("clk: zynqmp: Fix divider calculation")
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Signed-off-by: Amit Sunil Dhamne <amit.sunil.dhamne@xilinx.com>
---
 drivers/clk/zynqmp/divider.c | 17 ++++++++++++-----
 1 file changed, 12 insertions(+), 5 deletions(-)

diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c
index 5c41ddb..f7b3545 100644
--- a/drivers/clk/zynqmp/divider.c
+++ b/drivers/clk/zynqmp/divider.c
@@ -111,23 +111,30 @@ static unsigned long zynqmp_clk_divider_recalc_rate(s=
truct clk_hw *hw,

 static void zynqmp_get_divider2_val(struct clk_hw *hw,
                                    unsigned long rate,
-                                   unsigned long parent_rate,
                                    struct zynqmp_clk_divider *divider,
                                    int *bestdiv)
 {
        int div1;
        int div2;
        long error =3D LONG_MAX;
-       struct clk_hw *parent_hw =3D clk_hw_get_parent(hw);
-       struct zynqmp_clk_divider *pdivider =3D to_zynqmp_clk_divider(paren=
t_hw);
+       unsigned long div1_prate;
+       struct clk_hw *div1_parent_hw;
+       struct clk_hw *div2_parent_hw =3D clk_hw_get_parent(hw);
+       struct zynqmp_clk_divider *pdivider =3D
+                               to_zynqmp_clk_divider(div2_parent_hw);

        if (!pdivider)
                return;

+       div1_parent_hw =3D clk_hw_get_parent(div2_parent_hw);
+       if (!div1_parent_hw)
+               return;
+
+       div1_prate =3D clk_hw_get_rate(div1_parent_hw);
        *bestdiv =3D 1;
        for (div1 =3D 1; div1 <=3D pdivider->max_div;) {
                for (div2 =3D 1; div2 <=3D divider->max_div;) {
-                       long new_error =3D ((parent_rate / div1) / div2) - =
rate;
+                       long new_error =3D ((div1_prate / div1) / div2) - r=
ate;

                        if (abs(new_error) < abs(error)) {
                                *bestdiv =3D div2;
@@ -192,7 +199,7 @@ static long zynqmp_clk_divider_round_rate(struct clk_hw=
 *hw,
         */
        if (div_type =3D=3D TYPE_DIV2 &&
            (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
-               zynqmp_get_divider2_val(hw, rate, *prate, divider, &bestdiv=
);
+               zynqmp_get_divider2_val(hw, rate, divider, &bestdiv);
        }

        if ((clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) && divider->is_fra=
c)
--
2.7.4

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