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[23.128.96.18]) by mx.google.com with ESMTP id t13si3340989eds.358.2020.05.02.04.13.55; Sat, 02 May 2020 04:14:19 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@googlemail.com header.s=20161025 header.b=iyv5UYgz; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=googlemail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726900AbgEBLKQ (ORCPT + 99 others); Sat, 2 May 2020 07:10:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55700 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726548AbgEBLKP (ORCPT ); Sat, 2 May 2020 07:10:15 -0400 Received: from mail-ed1-x543.google.com (mail-ed1-x543.google.com [IPv6:2a00:1450:4864:20::543]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 180A2C061A0C; Sat, 2 May 2020 04:10:14 -0700 (PDT) Received: by mail-ed1-x543.google.com with SMTP id f12so9250264edn.12; Sat, 02 May 2020 04:10:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=UoFw4oXNAt1Ih5A43l+HKg/JC4jjYlQTF0HInppEBTw=; b=iyv5UYgzoKjin02wuvJurpyGnE+EonAc0gENZjTUAfOiF6FP9Ke6OJfGXCEHygVwlj hzdli9M11CRIQXySmtzp7pKsDk2vgJooumEYdR0GWbxhNxyEZ3arHa3T4BcJQu3Q5WGT oDNCKVijYMkRAGJz6455M/3aQ+aJSPPkdbq3kIlJEYNat6SQKLz9yEbGJUzBDW1I3e62 wjH1xklcDsKzvSn8Fpv17JlWiguKq+NyMII8JAd8H/0sE9Qr4HVDwBTURHX9E5DfGF71 BEG4px27S8XOwJwKEDV4CG9poe7eRJOc+VZV6bIIBdXUKyzZCMGN6T1cTkPUD8IRwdn1 5GOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=UoFw4oXNAt1Ih5A43l+HKg/JC4jjYlQTF0HInppEBTw=; b=l3R41Q3xKMwpUQ+00iZIzWUUd+xT2bXc9KX5QsLFJfB8O7vvsbKFTzFvkMoMc/WbTf vhdPBlDozlcppL0h+70pRYVAPVAhHOJs/fd85d3B/Q9w0LmisxTz30zi+L59eJKaF8ZV /S1RMfSHjfYoQILR7LKdNKVviJE63KCfK/3cfQo/B/MNtrFJJzvSS/EitvQJAmM/AA73 1Gt7H+8ubHgH+/vn+fi9GVm5DDOE2vmcwscQxioqMvJ1BqS6tlVVBp0MuCl4vAV9/tae owQQ0xUrWAa3ohHEZS7BXixwVGFvyj1umxEZXft0ow7z7nbzeb8rCGCWF8Xb8oQlys4N fR+Q== X-Gm-Message-State: AGi0Puar2qCuaeB4zL8mKPkKXmVLpVIlIHadTszDEcqOSJa6G0wzOn9h oblneuywlk61VudgvnnzcDoad+fBUKn1yF1qWcg/DiiuK4w= X-Received: by 2002:a50:a985:: with SMTP id n5mr6969277edc.338.1588417812752; Sat, 02 May 2020 04:10:12 -0700 (PDT) MIME-Version: 1.0 References: In-Reply-To: From: Martin Blumenstingl Date: Sat, 2 May 2020 13:10:01 +0200 Message-ID: Subject: Re: Re: [PATCH] clk/meson: fixes memleak issue in init err branch To: =?UTF-8?B?6LW15Yab5aWO?= Cc: opensource.kernel@vivo.com, Neil Armstrong , Stephen Boyd , Kevin Hilman , linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, Jerome Brunet Content-Type: multipart/mixed; boundary="0000000000007c52a905a4a857a3" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --0000000000007c52a905a4a857a3 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Bernhard, On Thu, Apr 30, 2020 at 5:33 AM =E8=B5=B5=E5=86=9B=E5=A5=8E wrote: [...] > I am not sure whether my understanding is correct. > I feels that the failure of our module can not block the entire kernel fr= om starting. > Maybe we should throw an exception, clear the status, as "old way", > and continue to execute the kernel. I added a HACK right at the beginning of meson8b_clkc_init_common where I a= dded: if (true) return; // HACK: simulate an error when I then try to boot the resulting kernel there's silence after u-boot is done: Starting kernel ... (output stops here) This is expected, because the UART clock is provided by this clock controller. And since we didn't register it there will be no serial output. Then I added "earlycon" to the boot args and attached the output to this ma= il. The result is still not great, because only the early console is working. Also timer initialization (smp_twd) as well as SMP startup failed. All other peripherals also failed to probe, because almost everything on this SoC depends on this main clock controller (the two exceptions that I know are: the always-on remote processor and the DDR clock controller). I hope that this explains the behavior when the main clock and reset controllers are not registered (either due to my hack or if there's an actual error). Please let me know if you have more questions. Now I would like to hear your suggestion, how to handle errors in this driv= er! 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