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Subject: Re: [PATCH 0/3] Tegra194 HW Fixes
To:     Takashi Iwai <tiwai@suse.de>
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From:   Sameer Pujar <spujar@nvidia.com>
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On 5/4/2020 2:05 PM, Sameer Pujar wrote:
>
>
> On 5/4/2020 1:59 PM, Takashi Iwai wrote:
>> External email: Use caution opening links or attachments
>>
>>
>> On Mon, 04 May 2020 10:16:13 +0200,
>> Sameer Pujar wrote:
>>> This series proposes SW workarounds for Tegra194 HDA HW bugs.
>>> Following are the two issues seen:
>>> =C2=A0 1. GCAP register does not reflect true capability.
>>> =C2=A0=C2=A0=C2=A0=C2=A0 The actual number of SDO lines is "4", where a=
s it reflects "2".
>>> =C2=A0 2. With 4 SDO line configuration playback fails for,
>>> =C2=A0=C2=A0=C2=A0=C2=A0 44.1K/48K, 2-channel, 16-bps audio stream.
>>>
>>> After fixing [1], issue [2] is uncovered.
>>> As per recommendation by Tegra HW team the workarounds are pushed.
>>>
>>> Testing done
>>> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
>>> =C2=A0 * Verify GCAP register after registering HDA sound card
>>> =C2=A0 * Verify audio playback for 44.1K/48K, 2-channel, 16-bps.
>>>
>>> Sameer Pujar (3):
>>> =C2=A0=C2=A0 ALSA: hda/tegra: correct number of SDO lines for Tegra194
>>> =C2=A0=C2=A0 ALSA: hda: add member to store ratio for stripe control
>>> =C2=A0=C2=A0 ALSA: hda/tegra: workaround playback failure on Tegra194
>> Through a quick glance, all changes look good.
>>
>> Is the device already in market, i.e. it had hit users?=C2=A0 If yes, I'=
m
>> going to merge for 5.7, otherwise for 5.8.
>
> Yes the device is in the market. But has not been reported by end users.
> During internal resting this has been discovered. I am fine with=20
> merging this to 5.8.

To add, end users currently won't see this problem because things work=20
fine with 2-SDO lines. The issue is seen when Tegra194 is allowed to=20
utilize its actual capability of 4-SDO lines.
>
> Thanks,
> Sameer.
>>
>>
>> thanks,
>>
>> Takashi
>