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Subject: Re: [RFC PATCH v11 6/9] media: tegra: Add Tegra210 Video input driver
To:     Dmitry Osipenko <digetx@gmail.com>, <thierry.reding@gmail.com>,
        <jonathanh@nvidia.com>, <frankc@nvidia.com>, <hverkuil@xs4all.nl>,
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From:   Sowjanya Komatineni <skomatineni@nvidia.com>
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On 5/4/20 12:44 AM, Dmitry Osipenko wrote:
> 30.04.2020 01:00, Sowjanya Komatineni =D0=BF=D0=B8=D1=88=D0=B5=D1=82:
>> +/*
>> + * VI channel input data type enum.
>> + * These data type enum value gets programmed into corresponding Tegra =
VI
>> + * channel register bits.
>> + */
>> +enum tegra_image_dt {
>> +	TEGRA_IMAGE_DT_YUV420_8 =3D 24,
>> +	TEGRA_IMAGE_DT_YUV420_10,
>> +
>> +	TEGRA_IMAGE_DT_YUV420CSPS_8 =3D 28,
>> +	TEGRA_IMAGE_DT_YUV420CSPS_10,
>> +	TEGRA_IMAGE_DT_YUV422_8,
>> +	TEGRA_IMAGE_DT_YUV422_10,
>> +	TEGRA_IMAGE_DT_RGB444,
>> +	TEGRA_IMAGE_DT_RGB555,
>> +	TEGRA_IMAGE_DT_RGB565,
>> +	TEGRA_IMAGE_DT_RGB666,
>> +	TEGRA_IMAGE_DT_RGB888,
>> +
>> +	TEGRA_IMAGE_DT_RAW6 =3D 40,
>> +	TEGRA_IMAGE_DT_RAW7,
>> +	TEGRA_IMAGE_DT_RAW8,
>> +	TEGRA_IMAGE_DT_RAW10,
>> +	TEGRA_IMAGE_DT_RAW12,
>> +	TEGRA_IMAGE_DT_RAW14,
>> +};
> Are these format IDs common to all Tegra SoCs or they unique to T210?
Common for all SoCs