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[76.210.143.223]) by smtp.gmail.com with ESMTPSA id 14sm86208pfy.38.2020.05.04.15.10.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 May 2020 15:10:11 -0700 (PDT) Date: Mon, 04 May 2020 15:10:11 -0700 (PDT) X-Google-Original-Date: Mon, 04 May 2020 15:09:13 PDT (-0700) Subject: Re: [PATCH 1/2] riscv: defconfig: enable spi nor on Hifive Unleashed A00 board. In-Reply-To: <1588240732-13905-2-git-send-email-sagar.kadam@sifive.com> CC: tudor.ambarus@microchip.com, miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com, Paul Walmsley , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, sagar.kadam@sifive.com From: Palmer Dabbelt To: sagar.kadam@sifive.com Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 30 Apr 2020 02:58:51 PDT (-0700), sagar.kadam@sifive.com wrote: > Enable MTD based SPI-NOR framework in order to use spi flash > available on HiFive Unleashed A00 board. > > Signed-off-by: Sagar Shrikant Kadam > --- > arch/riscv/configs/defconfig | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig > index 4da4886..970580b 100644 > --- a/arch/riscv/configs/defconfig > +++ b/arch/riscv/configs/defconfig > @@ -80,6 +80,8 @@ CONFIG_USB_STORAGE=y > CONFIG_USB_UAS=y > CONFIG_MMC=y > CONFIG_MMC_SPI=y > +CONFIG_MTD=y > +CONFIG_MTD_SPI_NOR=y > CONFIG_RTC_CLASS=y > CONFIG_VIRTIO_PCI=y > CONFIG_VIRTIO_BALLOON=y From the second patch's description I'm assuming that MTD still functions correctly without that change?