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Subject: Re: [PATCH] drm/bridge: ti-sn65dsi86: Implement lane reordering + polarity
From:   Stephen Boyd <swboyd@chromium.org>
Cc:     robdclark@chromium.org, seanpaul@chromium.org,
        linux-arm-msm@vger.kernel.org,
        Douglas Anderson <dianders@chromium.org>,
        Daniel Vetter <daniel@ffwll.ch>,
        David Airlie <airlied@linux.ie>,
        Jernej Skrabec <jernej.skrabec@siol.net>,
        Jonas Karlman <jonas@kwiboo.se>,
        dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org
To:     Andrzej Hajda <a.hajda@samsung.com>,
        Douglas Anderson <dianders@chromium.org>,
        Laurent Pinchart <Laurent.pinchart@ideasonboard.com>,
        Neil Armstrong <narmstrong@baylibre.com>
Date:   Mon, 04 May 2020 22:44:17 -0700
Message-ID: <158865745768.11125.12003632060774071567@swboyd.mtv.corp.google.com>
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Sender: linux-kernel-owner@vger.kernel.org
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Quoting Douglas Anderson (2020-05-04 21:36:31)
> The ti-sn65dsi86 MIPI DSI to eDP bridge chip supports arbitrary
> remapping of eDP lanes and also polarity inversion.  Both of these
> features have been described in the device tree bindings for the
> device since the beginning but were never implemented in the driver.
> Implement both of them.
>=20
> Part of this change also allows you to (via the same device tree
> bindings) specify to use fewer than the max number of DP lanes that
> the panel reports.  This could be useful if your display supports more
> lanes but only a few are hooked up on your board.
>=20
> Signed-off-by: Douglas Anderson <dianders@chromium.org>
> ---

Except for one thing below:

Reviewed-by: Stephen Boyd <swboyd@chromium.org>

> diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/brid=
ge/ti-sn65dsi86.c
> index 1a125423eb07..52cca54b525f 100644
> --- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c
> +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
> @@ -707,26 +716,20 @@ static void ti_sn_bridge_enable(struct drm_bridge *=
bridge)
>         int dp_rate_idx;
>         unsigned int val;
>         int ret =3D -EINVAL;
> +       int max_dp_lanes;
> =20
> -       /*
> -        * Run with the maximum number of lanes that the DP sink supports.
> -        *
> -        * Depending use cases, we might want to revisit this later becau=
se:
> -        * - It's plausible that someone may have run fewer lines to the
> -        *   sink than the sink actually supports, assuming that the lines
> -        *   will just be driven at a higher rate.
> -        * - The DP spec seems to indicate that it's more important to mi=
nimize
> -        *   the number of lanes than the link rate.
> -        *
> -        * If we do revisit, it would be important to measure the power i=
mpact.
> -        */
> -       pdata->dp_lanes =3D ti_sn_get_max_lanes(pdata);
> +       max_dp_lanes =3D ti_sn_get_max_lanes(pdata);
> +       pdata->dp_lanes =3D min(pdata->dp_lanes, max_dp_lanes);
> =20
>         /* DSI_A lane config */
>         val =3D CHA_DSI_LANES(4 - pdata->dsi->lanes);

Not a problem in this patch, but maybe this can be SN_MAX_DP_LANES -
pdata->dsi->lanes now.

>         regmap_update_bits(pdata->regmap, SN_DSI_LANES_REG,
>                            CHA_DSI_LANES_MASK, val);
> =20
> +       regmap_write(pdata->regmap, SN_LN_ASSIGN_REG, pdata->ln_assign);
> +       regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, LN_POLRS_MASK,
> +                          pdata->ln_polrs << LN_POLRS_OFFSET);
> +
>         /* set dsi clk frequency value */
>         ti_sn_bridge_set_dsi_rate(pdata);
> =20
> @@ -1063,6 +1066,50 @@ static int ti_sn_setup_gpio_controller(struct ti_s=
n_bridge *pdata)
>         return ret;
>  }
> =20
> +static void ti_sn_bridge_parse_lanes(struct ti_sn_bridge *pdata,
> +                                    struct device_node *np)
> +{
> +       u32 lane_assignments[SN_MAX_DP_LANES] =3D { 0, 1, 2, 3 };
> +       u32 lane_polarities[SN_MAX_DP_LANES] =3D { };
> +       struct device_node *endpoint;
> +       u8 ln_assign =3D 0;
> +       u8 ln_polrs =3D 0;

Do we need to assign to 0 to start? Seems like no?

> +       int dp_lanes;
> +       int i;
> +
> +       /*
> +        * Read config from the device tree about lane remapping and lane
> +        * polarities.  These are optional and we assume identity map and
> +        * normal polarity if nothing is specified.  It's OK to specify j=
ust
> +        * data-lanes but not lane-polarities but not vice versa.
> +        */
> +       endpoint =3D of_graph_get_endpoint_by_regs(np, 1, -1);
> +       dp_lanes =3D of_property_count_u32_elems(endpoint, "data-lanes");
> +       if (dp_lanes > 0) {
> +               of_property_read_u32_array(endpoint, "data-lanes",
> +                                          lane_assignments, dp_lanes);
> +               of_property_read_u32_array(endpoint, "lane-polarities",
> +                                          lane_polarities, dp_lanes);
> +       } else {
> +               dp_lanes =3D SN_MAX_DP_LANES;
> +       }

Needs an of_node_put(endpoint) here for the
of_graph_get_endpoint_by_regs() above.

> +
> +       /*
> +        * Convert into register format.  Loop over all lanes even if
> +        * data-lanes had fewer elements so that we nicely initialize
> +        * the LN_ASSIGN register.
> +        */
> +       for (i =3D SN_MAX_DP_LANES - 1; i >=3D 0; i--) {
> +               ln_assign =3D ln_assign << LN_ASSIGN_WIDTH | lane_assignm=
ents[i];
> +               ln_polrs =3D ln_polrs << 1 | lane_polarities[i];
> +       }
> +
> +       /* Stash in our struct for when we power on */
> +       pdata->dp_lanes =3D dp_lanes;
> +       pdata->ln_assign =3D ln_assign;
> +       pdata->ln_polrs =3D ln_polrs;
> +}