Received: by 2002:a25:23cc:0:0:0:0:0 with SMTP id j195csp544328ybj; Tue, 5 May 2020 03:31:24 -0700 (PDT) X-Google-Smtp-Source: APiQypK3ExoCWkJGxnZIF/qpyhe+pmrcyG4MuyoMLNhKGBrOQAesVfiy6tKYSN8ROa+6+zzpy+1l X-Received: by 2002:a17:906:1292:: with SMTP id k18mr2001254ejb.132.1588674683862; Tue, 05 May 2020 03:31:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1588674683; cv=none; d=google.com; s=arc-20160816; b=PiydeCBG9kWtJq1Da/yEkKQgwvf4o9Q1wRyPRiP2N2WhEsndJvuZ8eUMMGR4KVvHNM dlkNCEPE4LkJfKkUR2gKtVrNIVhDOJsxth5ixdzFCozKu7Dovjs771E0wRShHXF5G6Zr m8rrdyAQ9RvUO528CZoAzgc0jxMtpruFE6zgOb/xEuTz8BnXdI4q3ZSHGx+YhQYGxtEf 5IUDOguV1ataOnBWHVtxfMAvkAOQyHBsLPO2iFVzQTy4xAdeVV88Z4G+jKC9atSh+At5 gyVR/pdIK2IzdASDQ8PU775898NuS8eV25R6Tl7SL4KPjBf2F4Jxn/uoxWkeOfJEzRQU AjfA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:user-agent:in-reply-to :content-disposition:mime-version:references:message-id:subject:cc :to:from:date; bh=PJTmhwh3e4np2WHrXfexG7KkdODMQFVeMHb/gtEldOg=; b=SV+6c7FlocBjFCI5v630QALShQJH4wwzNi5SccCBXf1ts3ANJVBP2NEA9yUYrWNMr5 gxji255XZ00dJNNfi3dOp2coSyp9vmt+IYdYTpzB7hcGj1JLEUhcfWUYrKmMSwM6uvSW HDZVfYqyix9n2XJlCJINqluAKMptiEO0ExMiJHzCv/OWttntyIMNnG5ON9355WYJo4wv k3673Gn566ca/QZ8//dTflgcKFwle9CTOi4YEsaStBWSH1TG3tN93Ab3dAqtwSz6Dgdp GTAvxtT9UGvGw4fnzZJ/8zpl6BcpI0rb44ERlUR2Pb0QjfnBBwYQi9tBUgOAFRBbN0BM uZIA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id o25si953701ejh.73.2020.05.05.03.31.01; Tue, 05 May 2020 03:31:23 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728675AbgEEK3i (ORCPT + 99 others); Tue, 5 May 2020 06:29:38 -0400 Received: from foss.arm.com ([217.140.110.172]:36652 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725766AbgEEK3h (ORCPT ); Tue, 5 May 2020 06:29:37 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D081A30E; Tue, 5 May 2020 03:29:36 -0700 (PDT) Received: from e121166-lin.cambridge.arm.com (e121166-lin.cambridge.arm.com [10.1.196.255]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 982673F305; Tue, 5 May 2020 03:29:35 -0700 (PDT) Date: Tue, 5 May 2020 11:29:33 +0100 From: Lorenzo Pieralisi To: Alan Mikhak , jingoohan1@gmail.com, gustavo.pimentel@synopsys.com Cc: linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, amurray@thegoodpenguin.co.uk, bhelgaas@google.com, kishon@ti.com, paul.walmsley@sifive.com Subject: Re: [PATCH] PCI: dwc: Program outbound ATU upper limit register Message-ID: <20200505102933.GD12543@e121166-lin.cambridge.arm.com> References: <1585785493-23210-1-git-send-email-alan.mikhak@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1585785493-23210-1-git-send-email-alan.mikhak@sifive.com> User-Agent: Mutt/1.9.4 (2018-02-28) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Apr 01, 2020 at 04:58:13PM -0700, Alan Mikhak wrote: > From: Alan Mikhak > > Function dw_pcie_prog_outbound_atu_unroll() does not program the upper > 32-bit ATU limit register. Since ATU programming functions limit the > size of the translated region to 4GB by using a u32 size parameter, > these issues may combine into undefined behavior for resource sizes > with non-zero upper 32-bits. > > For example, a 128GB address space starting at physical CPU address of > 0x2000000000 with size of 0x2000000000 needs the following values > programmed into the lower and upper 32-bit limit registers: > 0x3fffffff in the upper 32-bit limit register > 0xffffffff in the lower 32-bit limit register > > Currently, only the lower 32-bit limit register is programmed with a > value of 0xffffffff but the upper 32-bit limit register is not being > programmed. As a result, the upper 32-bit limit register remains at its > default value after reset of 0x0. > > These issues may combine to produce undefined behavior since the ATU > limit address may be lower than the ATU base address. Programming the > upper ATU limit address register prevents such undefined behavior despite > the region size getting truncated due to the 32-bit size limit. > > Signed-off-by: Alan Mikhak > --- > drivers/pci/controller/dwc/pcie-designware.c | 7 +++++-- > drivers/pci/controller/dwc/pcie-designware.h | 3 ++- > 2 files changed, 7 insertions(+), 3 deletions(-) I would appreciate some feedback and possibly and ACK from DWC maintainers. Should this go to stable kernels ? It seems so, let me know if we want to add a stable tag. I will merge it, along with: https://patchwork.kernel.org/patch/11468465/ Lorenzo > > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c > index 681548c88282..c92496e36fd5 100644 > --- a/drivers/pci/controller/dwc/pcie-designware.c > +++ b/drivers/pci/controller/dwc/pcie-designware.c > @@ -244,13 +244,16 @@ static void dw_pcie_prog_outbound_atu_unroll(struct dw_pcie *pci, int index, > u64 pci_addr, u32 size) > { > u32 retries, val; > + u64 limit_addr = cpu_addr + size - 1; > > dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_BASE, > lower_32_bits(cpu_addr)); > dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_BASE, > upper_32_bits(cpu_addr)); > - dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LIMIT, > - lower_32_bits(cpu_addr + size - 1)); > + dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_LIMIT, > + lower_32_bits(limit_addr)); > + dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_LIMIT, > + upper_32_bits(limit_addr)); > dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET, > lower_32_bits(pci_addr)); > dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET, > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h > index a22ea5982817..5ce1aef706c5 100644 > --- a/drivers/pci/controller/dwc/pcie-designware.h > +++ b/drivers/pci/controller/dwc/pcie-designware.h > @@ -112,9 +112,10 @@ > #define PCIE_ATU_UNR_REGION_CTRL2 0x04 > #define PCIE_ATU_UNR_LOWER_BASE 0x08 > #define PCIE_ATU_UNR_UPPER_BASE 0x0C > -#define PCIE_ATU_UNR_LIMIT 0x10 > +#define PCIE_ATU_UNR_LOWER_LIMIT 0x10 > #define PCIE_ATU_UNR_LOWER_TARGET 0x14 > #define PCIE_ATU_UNR_UPPER_TARGET 0x18 > +#define PCIE_ATU_UNR_UPPER_LIMIT 0x20 > > /* > * The default address offset between dbi_base and atu_base. Root controller > -- > 2.7.4 >