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[23.128.96.18]) by mx.google.com with ESMTP id l21si1114109eds.265.2020.05.05.04.34.49; Tue, 05 May 2020 04:35:13 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gwQiB1gV; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728806AbgEELd0 (ORCPT + 99 others); Tue, 5 May 2020 07:33:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51574 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1728733AbgEELd0 (ORCPT ); Tue, 5 May 2020 07:33:26 -0400 Received: from mail-vs1-xe43.google.com (mail-vs1-xe43.google.com [IPv6:2607:f8b0:4864:20::e43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 291AEC061A0F for ; Tue, 5 May 2020 04:33:26 -0700 (PDT) Received: by mail-vs1-xe43.google.com with SMTP id m24so994832vsq.10 for ; Tue, 05 May 2020 04:33:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=aW3lDGiADWs7JW9cxGTC8AY/7i0BQSigJub/cuiuwnI=; b=gwQiB1gVTJOghuOSOjL5cVHiwLy0rFkim78R7G2TC6F+hsHSwnidTIKVzx5klHJ7YG SIRFog74RlxFwXxnapCTCiNXZ4ohqiDY8CEOcnTliPMuDXg1n+BRFTVaJoGAWu3k30rq 4mTAmNf7HdW16nfyEwSTy/j+IEKOz/Z5EdgS9LOz9Q7/aIF4OXi/zXryZFQTXnS5kNzB ttSuzVw2u3gm9ZQA4oE3o0oMx7tLrYRkDdJid37BJ+dugHdK17yzBPzDO6RZTdThjCT1 uZ74y5/ZJQ2vlXfetxdiqjHX3KHYW3meAgxWIcCB/2GGn3pnV6qhknYnPJNq1+qXR/CO 5CmQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=aW3lDGiADWs7JW9cxGTC8AY/7i0BQSigJub/cuiuwnI=; b=V8K7/mtyHcKkK0SFfLRM3415yi2zTQG56DYuwIdGEUdHUb74K+7f9l6fDKQpma1IJo mRIcSX2MAHQo6ntEAFCNoZ29HKOPmbqUCN3uGaXvmJwcSkmOXc7flu83hppAkw0Dm3PG h/O94s0HvqglIgjnUrLGI1ieykjjSsgsoy3rB2Fmx25BZZ5mS+pWTrnVB6Kd7ThjcPxM M9oKSoJJXPaepIwR0iKhsqVqjLNwfjMhpsA++KQbep0+jSmzTCSpi7RDM68Z23szeWf5 wJA06x67zWf/2hwtYzLMlDGFlvvzIyG5EJWxHCsBSDHPMJeX1rFLO7bCmqCtISxydV/3 MQ2Q== X-Gm-Message-State: AGi0Pua6MxX81aQtLzd9ZUbLdGB5NN14Vv6ys2GiNW8D/Mcs6JGMYAsa dimiWwZNZ/nn3yuj/ALPlJimJxpFt7v8kmM1vxdtgQ== X-Received: by 2002:a67:ead1:: with SMTP id s17mr2269661vso.200.1588678405301; Tue, 05 May 2020 04:33:25 -0700 (PDT) MIME-Version: 1.0 References: <20200427103048.20785-1-benchuanggli@gmail.com> In-Reply-To: <20200427103048.20785-1-benchuanggli@gmail.com> From: Ulf Hansson Date: Tue, 5 May 2020 13:32:49 +0200 Message-ID: Subject: Re: [PATCH] mmc: sdhci-pci-gli: Fix no irq handler from suspend To: Ben Chuang Cc: Adrian Hunter , "linux-mmc@vger.kernel.org" , Linux Kernel Mailing List , Ben Chuang , Renius.Chen@genesyslogic.com.tw, vineethrp@gmail.com, dflogeras2@gmail.com Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 27 Apr 2020 at 12:30, Ben Chuang wrote: > > From: Ben Chuang > > The kernel prints a message similar to > "[ 28.881959] do_IRQ: 5.36 No irq handler for vector" > when GL975x resumes from suspend. Implement a resume callback to fix this. > > Fixes: 31e43f31890c ("mmc: sdhci-pci-gli: Enable MSI interrupt for GL975x") > Co-developed-by: Renius Chen > Signed-off-by: Renius Chen > Tested-by: Dave Flogeras > Signed-off-by: Ben Chuang Applied for fixes, thanks! Kind regards Uffe > --- > drivers/mmc/host/sdhci-pci-gli.c | 18 ++++++++++++++++++ > 1 file changed, 18 insertions(+) > > diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c > index ce15a05f23d4..7195dd33ac3d 100644 > --- a/drivers/mmc/host/sdhci-pci-gli.c > +++ b/drivers/mmc/host/sdhci-pci-gli.c > @@ -334,6 +334,18 @@ static u32 sdhci_gl9750_readl(struct sdhci_host *host, int reg) > return value; > } > > +#ifdef CONFIG_PM_SLEEP > +int sdhci_pci_gli_resume(struct sdhci_pci_chip *chip) > +{ > + struct sdhci_pci_slot *slot = chip->slots[0]; > + > + pci_free_irq_vectors(slot->chip->pdev); > + gli_pcie_enable_msi(slot); > + > + return sdhci_pci_resume_host(chip); > +} > +#endif > + > static const struct sdhci_ops sdhci_gl9755_ops = { > .set_clock = sdhci_set_clock, > .enable_dma = sdhci_pci_enable_dma, > @@ -348,6 +360,9 @@ const struct sdhci_pci_fixes sdhci_gl9755 = { > .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50, > .probe_slot = gli_probe_slot_gl9755, > .ops = &sdhci_gl9755_ops, > +#ifdef CONFIG_PM_SLEEP > + .resume = sdhci_pci_gli_resume, > +#endif > }; > > static const struct sdhci_ops sdhci_gl9750_ops = { > @@ -366,4 +381,7 @@ const struct sdhci_pci_fixes sdhci_gl9750 = { > .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50, > .probe_slot = gli_probe_slot_gl9750, > .ops = &sdhci_gl9750_ops, > +#ifdef CONFIG_PM_SLEEP > + .resume = sdhci_pci_gli_resume, > +#endif > }; > -- > 2.26.2 >