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Subject: Re: [PATCH v2 1/1] fs/splice: add missing callback for inaccessible
 pages
To:     Christian Borntraeger <borntraeger@de.ibm.com>,
        Ulrich Weigand <uweigand@de.ibm.com>
Cc:     Claudio Imbrenda <imbrenda@linux.ibm.com>, viro@zeniv.linux.org.uk,
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        peterz@infradead.org, sean.j.christopherson@intel.com,
        Ulrich.Weigand@de.ibm.com
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Message-ID: <6e97a4b0-df4f-90c7-a6f7-61ee52e0833e@intel.com>
Date:   Tue, 5 May 2020 07:24:18 -0700
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On 5/5/20 7:00 AM, Christian Borntraeger wrote:
> We are certainly not married to our approach. I would happily extend/change
> this to anything that works for your case and the s390 case. So can you outline
> your requirements a bit more?

For SEV, the guest define which pages are encrypted or not.  You could
theoretically do DMA to them or have the CPU access their contents, but
you'd get either get ciphertext for reads, or data corruption and loss
of cache coherency for writes.  That's not so cool.

Ideally, we would stop the CPU from ever accessing those pages by
unmapping them.  But, the pages go in and out of the encrypted state and
the host really needs to be *sure* about what's going on before it
restores its mapping and messes with the page.  That includes situations
where someone does a gup, starts an I/O to an unencrypted page, then the
guest tries to convert that page over to being encrypted.

So, the requirements are:

1. Allow host-side DMA and CPU access to shared pages
2. Stop host-side DMA and CPU access to encrypted pages
3. Allow pages to be converted between the states at the request of the
   guest

Stopping the DMA is pretty easy, even across the gazillions of drivers
in the tree because even random ethernet drivers do stuff like:

                txdr->buffer_info[i].dma =
                        dma_map_single(&pdev->dev, skb->data, skb->len,
                                       DMA_TO_DEVICE);

So the DMA can be stopped at the mapping layer.  It's a *LOT* easier to
catch there since the IOMMUs already provide isolation between the I/O
and CPU address spaces.