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From:   Reinette Chatre <reinette.chatre@intel.com>
To:     tglx@linutronix.de, fenghua.yu@intel.com, bp@alien8.de,
        tony.luck@intel.com
Cc:     kuo-lang.tseng@intel.com, mingo@redhat.com, babu.moger@amd.com,
        hpa@zytor.com, x86@kernel.org, linux-kernel@vger.kernel.org,
        Reinette Chatre <reinette.chatre@intel.com>
Subject: [PATCH V2 0/7] x86/resctrl: Support wider MBM counters
Date:   Tue,  5 May 2020 15:36:11 -0700
Message-Id: <cover.1588715690.git.reinette.chatre@intel.com>
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V1 submission available from:
https://lore.kernel.org/lkml/cover.1585763047.git.reinette.chatre@intel.com

Changes since V1:
- Add four new preparatory patches to this series to eliminate the
  unnecessary reading of monitoring properties from every CPU (reading from
  one CPU is sufficient) and remove some unnecessary existing code:
  - Rename resctrl_sched.h to resctrl.h because it will no longer be
    dedicated to work done during scheduling.(Borislav)
  - Move functions reading the monitoring properties via CPUID to
    resctrl subsystem, continue calling them from common CPU code.(Borislav)
  - Read monitoring CPU properties once, no longer from every CPU.(Borislav)
  - Remove unnecessary sanity checks on properties read from CPU.(Borislav)
- Split (1) obtaining the new enumerable MBM counter width from the
  system and (2) using it within resctrl into two patches.

Below is from V1 submission:

Memory Bandwidth Monitoring (MBM) is an Intel Resource Director
Technology (RDT) feature that tracks Total and Local bandwidth
generated which misses the L3 cache.

The original Memory Bandwidth Monitoring (MBM) architectural
definition defines counters of up to 62 bits and the first-generation
MBM implementation uses 24 bit counters. Software is required to poll
at 1 second or faster to ensure that data is retrieved before a counter
rollover occurs more than once under worst conditions.

As system bandwidths scale the software requirement is maintained with
the introduction of a per-resource enumerable MBM counter width.

This series adds support for the new enumerable MBM counter width.

Details about the feature can be found in Chapter 9 of the most
recent Intel ISE available from
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf

Reinette Chatre (7):
  x86/resctrl: Rename asm/resctrl_sched.h to asm/resctrl.h
  x86/cpu: Move resctrl CPUID code to resctrl
  x86/resctrl: Remove unnecessary RMID checks
  x86/resctrl: Query LLC monitoring properties once during boot
  x86/resctrl: Maintain MBM counter width per resource
  x86/resctrl: Support CPUID enumeration of MBM counter width
  x86/resctrl: Support wider MBM counters

 MAINTAINERS                                   |  2 +-
 arch/x86/include/asm/processor.h              |  3 +-
 .../asm/{resctrl_sched.h => resctrl.h}        |  9 +++--
 arch/x86/kernel/cpu/amd.c                     |  3 ++
 arch/x86/kernel/cpu/common.c                  | 40 -------------------
 arch/x86/kernel/cpu/intel.c                   |  7 ++++
 arch/x86/kernel/cpu/resctrl/core.c            | 32 ++++++++++++++-
 arch/x86/kernel/cpu/resctrl/ctrlmondata.c     |  8 ++--
 arch/x86/kernel/cpu/resctrl/internal.h        | 15 +++++--
 arch/x86/kernel/cpu/resctrl/monitor.c         | 27 +++++++++----
 arch/x86/kernel/cpu/resctrl/pseudo_lock.c     |  2 +-
 arch/x86/kernel/cpu/resctrl/rdtgroup.c        |  4 +-
 arch/x86/kernel/process_32.c                  |  2 +-
 arch/x86/kernel/process_64.c                  |  2 +-
 14 files changed, 91 insertions(+), 65 deletions(-)
 rename arch/x86/include/asm/{resctrl_sched.h => resctrl.h} (92%)

-- 
2.21.0