To: "Bryan O'Sullivan" <bos@pathscale.com>
Cc: rolandd@cisco.com, gregkh@suse.de, akpm@osdl.org, davem@davemloft.net,
       linux-kernel@vger.kernel.org, openib-general@openib.org
Subject: Re: [PATCH 7 of 20] ipath - misc driver support code
References: <2f16f504dd4b98c2ce7c.1141922820@localhost.localdomain>
From: Roland Dreier <rdreier@cisco.com>
Date: Thu, 09 Mar 2006 15:13:24 -0800
In-Reply-To: <2f16f504dd4b98c2ce7c.1141922820@localhost.localdomain> (Bryan O'Sullivan's message of "Thu,  9 Mar 2006 08:47:00 -0800")
Message-ID: <adau0a7fbzf.fsf@cisco.com>
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 > +/**
 > + * ipath_unordered_wc - indicate whether write combining is ordered
 > + *
 > + * Because our performance depends on our ability to do write combining mmio
 > + * writes in the most efficient way, we need to know if we are on an Intel
 > + * or AMD x86_64 processor.  AMD x86_64 processors flush WC buffers out in
 > + * the order completed, and so no special flushing is required to get
 > + * correct ordering.  Intel processors, however, will flush write buffers
 > + * out in "random" orders, and so explict ordering is needed at times.
 > + */
 > +int ipath_unordered_wc(void)
 > +{
 > +	return boot_cpu_data.x86_vendor == X86_VENDOR_INTEL;
 > +}

This is kind of theoritical, but it seems to me that it would be safer
to write this as

	int ipath_unordered_wc(void)
	{
		return boot_cpu_data.x86_vendor != X86_VENDOR_AMD;
	}

after all, Via is probably going to have an x86-64 CPU one of these
days, and I doubt you've checked that their WC flush is ordered.

 - R.
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