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[24.155.109.49]) by smtp.gmail.com with ESMTPSA id z13sm1621472oth.10.2020.05.07.13.27.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 May 2020 13:27:54 -0700 (PDT) Received: (nullmailer pid 21941 invoked by uid 1000); Thu, 07 May 2020 20:27:53 -0000 Date: Thu, 7 May 2020 15:27:53 -0500 From: Rob Herring To: Kishon Vijay Abraham I Cc: Tom Joseph , Bjorn Helgaas , Lorenzo Pieralisi , Andrew Murray , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 4/4] PCI: cadence: Fix to read 32-bit Vendor ID/Device ID property from DT Message-ID: <20200507202753.GA21833@bogus> References: <20200417114322.31111-1-kishon@ti.com> <20200417114322.31111-5-kishon@ti.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200417114322.31111-5-kishon@ti.com> User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, 17 Apr 2020 17:13:22 +0530, Kishon Vijay Abraham I wrote: > The PCI Bus Binding specification (IEEE Std 1275-1994 Revision 2.1 [1]) > defines both Vendor ID and Device ID to be 32-bits. Fix > pcie-cadence-host.c driver to read 32-bit Vendor ID and Device ID > properties from device tree. > > [1] -> https://www.devicetree.org/open-firmware/bindings/pci/pci2_1.pdf > > Signed-off-by: Kishon Vijay Abraham I > --- > drivers/pci/controller/cadence/pcie-cadence-host.c | 4 ++-- > drivers/pci/controller/cadence/pcie-cadence.h | 4 ++-- > 2 files changed, 4 insertions(+), 4 deletions(-) > Acked-by: Rob Herring