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([2001:b07:6468:f312:20ea:bae4:47a7:31db]) by smtp.gmail.com with ESMTPSA id z1sm12491316wmf.15.2020.05.08.02.50.56 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 08 May 2020 02:50:57 -0700 (PDT) Subject: Re: [PATCH v3] KVM: x86/pmu: Support full width counting To: Like Xu Cc: Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Joerg Roedel , kvm@vger.kernel.org, linux-kernel@vger.kernel.org References: <20200508083218.120559-1-like.xu@linux.intel.com> From: Paolo Bonzini Message-ID: Date: Fri, 8 May 2020 11:50:56 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.6.0 MIME-Version: 1.0 In-Reply-To: <20200508083218.120559-1-like.xu@linux.intel.com> Content-Type: text/plain; charset=windows-1252 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org I would just do small changes to the validity checks for MSRs. On 08/05/20 10:32, Like Xu wrote: > return 0; > + case MSR_IA32_PERF_CAPABILITIES: > + *data = vcpu->arch.perf_capabilities; > + return 0; This should be: if (!msr_info->host_initiated && !guest_cpuid_has(vcpu, X86_FEATURE_PDCM)) return 1; > default: > - if ((pmc = get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0))) { > + if ((pmc = get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0)) || > + (pmc = get_gp_pmc(pmu, msr, MSR_IA32_PMC0))) { > u64 val = pmc_read_counter(pmc); > *data = val & pmu->counter_bitmask[KVM_PMC_GP]; > return 0; > @@ -258,9 +277,21 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) > return 0; > } > break; > + case MSR_IA32_PERF_CAPABILITIES: > + if (msr_info->host_initiated && > + !(data & ~vmx_get_perf_capabilities())) { Likewise: if (!msr->info->host_initiated) return 1; if (guest_cpuid_has(vcpu, X86_FEATURE_PDCM)) ? data & ~vmx_get_perf_capabilities() : data) return 1; Otherwise looks good, I'm going to queue this. Paolo