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Date:   Fri, 8 May 2020 14:43:30 +0300
From:   Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To:     Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc:     Vinod Koul <vkoul@kernel.org>, Viresh Kumar <vireshk@kernel.org>,
        Dan Williams <dan.j.williams@intel.com>,
        Serge Semin <fancer.lancer@gmail.com>,
        Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>,
        Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
        Paul Burton <paulburton@kernel.org>,
        Ralf Baechle <ralf@linux-mips.org>,
        Arnd Bergmann <arnd@arndb.de>,
        Rob Herring <robh+dt@kernel.org>, linux-mips@vger.kernel.org,
        devicetree@vger.kernel.org, dmaengine@vger.kernel.org,
        linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 6/6] dmaengine: dw: Take HC_LLP flag into account for
 noLLP auto-config
Message-ID: <20200508114330.GL185537@smile.fi.intel.com>
References: <20200306131048.ADBE18030797@mail.baikalelectronics.ru>
 <20200508105304.14065-1-Sergey.Semin@baikalelectronics.ru>
 <20200508105304.14065-7-Sergey.Semin@baikalelectronics.ru>
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On Fri, May 08, 2020 at 01:53:04PM +0300, Serge Semin wrote:
> Full multi-block transfers functionality is enabled in DW DMA
> controller only if CHx_MULTI_BLK_EN is set. But LLP-based transfers
> can be executed only if hardcode channel x LLP register feature isn't
> enabled, which can be switched on at the IP core synthesis for
> optimization. If it's enabled then the LLP register is hardcoded to
> zero, so the blocks chaining based on the LLPs is unsupported.
> 

This one is good.

Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>

Feel free to reassemble the series, so, Vinod can apply it independently.

> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> Cc: Paul Burton <paulburton@kernel.org>
> Cc: Ralf Baechle <ralf@linux-mips.org>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Cc: Dan Williams <dan.j.williams@intel.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: linux-mips@vger.kernel.org
> Cc: devicetree@vger.kernel.org
> 
> ---
> 
> Changelog v2:
> - Rearrange SoBs.
> - Add comment about why hardware accelerated LLP list support depends
>   on both MBLK_EN and HC_LLP configs setting.
> - Use explicit bits state comparison operator.
> ---
>  drivers/dma/dw/core.c | 11 ++++++++++-
>  drivers/dma/dw/regs.h |  1 +
>  2 files changed, 11 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c
> index 5b76ccc857fd..3179d45df662 100644
> --- a/drivers/dma/dw/core.c
> +++ b/drivers/dma/dw/core.c
> @@ -1180,8 +1180,17 @@ int do_dma_probe(struct dw_dma_chip *chip)
>  			 */
>  			dwc->block_size =
>  				(4 << ((pdata->block_size >> 4 * i) & 0xf)) - 1;
> +
> +			/*
> +			 * According to the DW DMA databook the true scatter-
> +			 * gether LLPs aren't available if either multi-block
> +			 * config is disabled (CHx_MULTI_BLK_EN == 0) or the
> +			 * LLP register is hard-coded to zeros
> +			 * (CHx_HC_LLP == 1).
> +			 */
>  			dwc->nollp =
> -				(dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0;
> +				(dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0 ||
> +				(dwc_params >> DWC_PARAMS_HC_LLP & 0x1) == 1;
>  			dwc->max_burst =
>  				(0x4 << (dwc_params >> DWC_PARAMS_MSIZE & 0x7));
>  		} else {
> diff --git a/drivers/dma/dw/regs.h b/drivers/dma/dw/regs.h
> index f581d4809b71..a8af19d0eabd 100644
> --- a/drivers/dma/dw/regs.h
> +++ b/drivers/dma/dw/regs.h
> @@ -126,6 +126,7 @@ struct dw_dma_regs {
>  
>  /* Bitfields in DWC_PARAMS */
>  #define DWC_PARAMS_MSIZE	16		/* max group transaction size */
> +#define DWC_PARAMS_HC_LLP	13		/* set LLP register to zero */
>  #define DWC_PARAMS_MBLK_EN	11		/* multi block transfer */
>  
>  /* bursts size */
> -- 
> 2.25.1
> 

-- 
With Best Regards,
Andy Shevchenko