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Subject: Re: [PATCH 2/3] MIPS: Loongson: Add hwmon support for generic CPU
To:     Tiezhu Yang <yangtiezhu@loongson.cn>,
        Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
        Huacai Chen <chenhc@lemote.com>,
        Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc:     linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org,
        Xuefeng Li <lixuefeng@loongson.cn>
References: <1588938904-924-1-git-send-email-yangtiezhu@loongson.cn>
 <1588938904-924-3-git-send-email-yangtiezhu@loongson.cn>
From:   WANG Xuerui <kernel@xen0n.name>
Message-ID: <f7184121-c044-6e79-78ab-dcc9103b27c2@xen0n.name>
Date:   Fri, 8 May 2020 20:51:55 +0800
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On 2020/5/8 19:55, Tiezhu Yang wrote:

> Add PRID_IMP_LOONGSON_64G case to enable hwmon support for Loongson
> generic CPU such as 3A4000 and newer CPU.
>
> Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
> ---
>   drivers/platform/mips/cpu_hwmon.c | 1 +
>   1 file changed, 1 insertion(+)
>
> diff --git a/drivers/platform/mips/cpu_hwmon.c b/drivers/platform/mips/cpu_hwmon.c
> index add5f52..7b4bde1 100644
> --- a/drivers/platform/mips/cpu_hwmon.c
> +++ b/drivers/platform/mips/cpu_hwmon.c
> @@ -43,6 +43,7 @@ int loongson3_cpu_temp(int cpu)
>   		break;
>   	case PRID_REV_LOONGSON3A_R3_0:
>   	case PRID_REV_LOONGSON3A_R3_1:
> +	case PRID_IMP_LOONGSON_64G:
>   	default:
>   		reg = (reg & 0xffff)*731/0x4000 - 273;
>   		break;

Hi,

This is obviously wrong, as the value being matched is a PRID_REV. You 
can tell from the neighboring match arms.

Also, the LOONGSON_64G cores are 3A4000 and newer, that have CSR 
support. The csr_temp_enable flag is probed in loongson_hwmon_init, then 
the switch is simply never entered for these.