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From:   "Daniel Walker (danielwa)" <danielwa@cisco.com>
To:     Pratyush Yadav <me@yadavpratyush.com>
CC:     Tudor Ambarus <tudor.ambarus@microchip.com>,
        Vignesh Raghavendra <vigneshr@ti.com>,
        Richard Weinberger <richard@nod.at>,
        "xe-linux-external(mailer list)" <xe-linux-external@cisco.com>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "linux-mtd@lists.infradead.org" <linux-mtd@lists.infradead.org>,
        "Miquel Raynal" <miquel.raynal@bootlin.com>
Subject: Re: [RFC-PATCH] mtd: spi-nor: add conditional 4B opcodes
Thread-Topic: [RFC-PATCH] mtd: spi-nor: add conditional 4B opcodes
Thread-Index: AQHWJW7Z+Cwh12LwKkae6PRXuOQSAg==
Date:   Fri, 8 May 2020 19:28:27 +0000
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On Sat, May 09, 2020 at 12:37:35AM +0530, Pratyush Yadav wrote:
> Hi Daniel,
>=20
> On 07/05/20 06:13PM, Daniel Walker (danielwa) wrote:
> > On Thu, May 07, 2020 at 11:33:46PM +0530, Pratyush Yadav wrote:
> > > On 07/05/20 09:20AM, Daniel Walker wrote:
> > > > Some chips have 4B opcodes, but there is no way to know if they hav=
e
> > > > them. This device tree option allows platform owners to force enabl=
e 4b
> > > > opcodes when they know their chips support it even when it can be
> > > > automatically identified.
> > >=20
> > > Do you mean that two chips might have the same ID but one of them can=
=20
> > > support 4B opcodes and the other can not? Is it possible to detect th=
is=20
> > > in a fixup hook? I think it would be better to do something like this=
 in=20
> > > a fixup hook instead of via device tree.
> >  =20
> > Yes. The chip I added the option for is an example of this, it's n25q25=
6a. I'm not familiar with the
> > fixup hook mechanism, but I would assume you need some way to tell betw=
een the 4B
> > opcode chips and the non-4B opcode chips. For n25q256a, we have not fou=
nd a way
> > to do that.
>=20
> I'm assuming this patch is related to [0]. If all you want is to address=
=20
> memory above 16M, why not switch to 4-byte addressing mode instead?=20
> Taking a quick look at the datasheet tells me this can be done via the=20
> "Enter 4-byte address mode" command (0xB7). Then just use the regular=20
> read/program commands with 4-byte addresses. Does that work for you? Is=20
> there any reason you _have_ to use dedicated 4B opcodes?

It might, I don't think we need anything beyond access to move than 16M. Yo=
ur
proposal would be to have a hook which enters the 0xB7 command?

I guess the question would be do all the chips have this ability.

Daniel=