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From:   Bharat Kumar Gogada <bharatku@xilinx.com>
To:     Bjorn Helgaas <helgaas@kernel.org>
CC:     "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>,
        "bhelgaas@google.com" <bhelgaas@google.com>,
        "robh@kernel.org" <robh@kernel.org>,
        Ravikiran Gummaluri <rgummal@xilinx.com>
Subject: RE: [PATCH v7 2/2] PCI: xilinx-cpm: Add Versal CPM Root Port driver
Thread-Topic: [PATCH v7 2/2] PCI: xilinx-cpm: Add Versal CPM Root Port driver
Thread-Index: AQHWJGcFkx3tnPS0S0KeSN8z5DhGVaidCHuAgAWxoTA=
Date:   Mon, 11 May 2020 10:47:23 +0000
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 <20200507194939.GA21050@bjorn-Precision-5520>
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> Subject: Re: [PATCH v7 2/2] PCI: xilinx-cpm: Add Versal CPM Root Port dri=
ver
>=20
> On Thu, May 07, 2020 at 05:28:36PM +0530, Bharat Kumar Gogada wrote:
> > - Add support for Versal CPM as Root Port.
> > - The Versal ACAP devices include CCIX-PCIe Module (CPM). The integrate=
d
> >   block for CPM along with the integrated bridge can function
> >   as PCIe Root Port.
> > - Bridge error and legacy interrupts in Versal CPM are handled using
> >   Versal CPM specific interrupt line.
>=20
> > +static inline bool cpm_pcie_link_up(struct xilinx_cpm_pcie_port
> > +*port) {
> > +	return (pcie_read(port, XILINX_CPM_PCIE_REG_PSCR) &
> > +		XILINX_CPM_PCIE_REG_PSCR_LNKUP) ? 1 : 0;
>=20
> Almost all of the *_link_up() functions return "int".  I don't know if th=
ere's really
> any benefit to using "bool", but if you do, you should probably return "t=
rue" or
> "false" instead of 1/0.
Hi Bjorn, thanks will fix this.
>=20
> > +	port->irq_misc =3D platform_get_irq(pdev, 0);
> > +	if (port->irq_misc <=3D 0) {
>=20
> Use:
>=20
>   if (port->irq_misc < 0) {
>=20
> See https://lore.kernel.org/r/20200501224042.141366-3-helgaas@kernel.org
Agreed, will fix this.

Regards,
Bharat