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[24.155.109.49]) by smtp.gmail.com with ESMTPSA id c25sm3536777otp.50.2020.05.12.09.42.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 May 2020 09:42:34 -0700 (PDT) Received: (nullmailer pid 18148 invoked by uid 1000); Tue, 12 May 2020 16:42:33 -0000 Date: Tue, 12 May 2020 11:42:33 -0500 From: Rob Herring To: Jiaxun Yang Cc: maz@kernel.org, Thomas Gleixner , Jason Cooper , Huacai Chen , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mips@vger.kernel.org Subject: Re: [PATCH v3 2/6] dt-bindings: interrupt-controller: Add Loongson HTVEC Message-ID: <20200512164233.GB12151@bogus> References: <20200422142428.1249684-1-jiaxun.yang@flygoat.com> <20200501092139.2988670-1-jiaxun.yang@flygoat.com> <20200501092139.2988670-2-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200501092139.2988670-2-jiaxun.yang@flygoat.com> User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, May 01, 2020 at 05:21:33PM +0800, Jiaxun Yang wrote: > Add binding for Loongson-3 HyperTransport Interrupt Vector Controller. > > Signed-off-by: Jiaxun Yang > --- > .../interrupt-controller/loongson,htvec.yaml | 59 +++++++++++++++++++ > 1 file changed, 59 insertions(+) > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,htvec.yaml > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongson,htvec.yaml b/Documentation/devicetree/bindings/interrupt-controller/loongson,htvec.yaml > new file mode 100644 > index 000000000000..547a80c89eba > --- /dev/null > +++ b/Documentation/devicetree/bindings/interrupt-controller/loongson,htvec.yaml > @@ -0,0 +1,59 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: "http://devicetree.org/schemas/interrupt-controller/loongson,htvec.yaml#" > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" > + > +title: Loongson-3 HyperTransport Interrupt Vector Controller > + > +maintainers: > + - Jiaxun Yang > + > +allOf: > + - $ref: /schemas/interrupt-controller.yaml# Don't need this. It's already applied to any node named 'interrupt-controller'. > + > +description: | Can drop '|' if you don't need formatting. > + This interrupt controller is found in the Loongson-3 family of chips for > + receiving vectorized interrupts from PCH's interrupt controller. > + > +properties: > + compatible: > + const: loongson,htvec-1.0 > + > + reg: > + maxItems: 1 > + > + interrupts: > + minItems: 1 > + maxItems: 4 > + description: | > + Four parent interrupts that receive chained interrupts. > + > + interrupt-controller: true > + > + '#interrupt-cells': > + const: 1 > + > +required: > + - compatible > + - reg > + - interrupts > + - interrupt-controller > + - '#interrupt-cells' Add: additionalProperties: false > + > +examples: > + - | > + #include > + htvec: interrupt-controller@1fb000080 { Unit-address doesn't match reg. > + compatible = "loongson,htvec-1.0"; > + reg = <0xfb000080 0x40>; > + interrupt-controller; > + #interrupt-cells = <1>; > + > + interrupt-parent = <&liointc>; > + interrupts = <24 IRQ_TYPE_LEVEL_HIGH>, > + <25 IRQ_TYPE_LEVEL_HIGH>, > + <26 IRQ_TYPE_LEVEL_HIGH>, > + <27 IRQ_TYPE_LEVEL_HIGH>; > + }; > +... > -- > 2.26.0.rc2 >