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[2003:f1:3713:2e00:428d:5cff:feb9:9db8]) by smtp.googlemail.com with ESMTPSA id r3sm9724228wmh.48.2020.05.12.14.11.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 May 2020 14:11:23 -0700 (PDT) From: Martin Blumenstingl To: robh+dt@kernel.org, andrew@lunn.ch, f.fainelli@gmail.com, linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org Cc: jianxin.pan@amlogic.com, davem@davemloft.net, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Martin Blumenstingl Subject: [PATCH v3 7/8] net: stmmac: dwmac-meson8b: Make the clock enabling code re-usable Date: Tue, 12 May 2020 23:11:02 +0200 Message-Id: <20200512211103.530674-8-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200512211103.530674-1-martin.blumenstingl@googlemail.com> References: <20200512211103.530674-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The timing adjustment clock will need similar logic as the RGMII clock: It has to be enabled in the driver conditionally and when the driver is unloaded it should be disabled again. Extract the existing code for the RGMII clock into a new function so it can be re-used. Reviewed-by: Andrew Lunn Signed-off-by: Martin Blumenstingl --- .../ethernet/stmicro/stmmac/dwmac-meson8b.c | 23 +++++++++++++++---- 1 file changed, 18 insertions(+), 5 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c index 41f3ef6bea66..d31f79c455de 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c @@ -266,6 +266,22 @@ static int meson_axg_set_phy_mode(struct meson8b_dwmac *dwmac) return 0; } +static int meson8b_devm_clk_prepare_enable(struct meson8b_dwmac *dwmac, + struct clk *clk) +{ + int ret; + + ret = clk_prepare_enable(clk); + if (ret) + return ret; + + devm_add_action_or_reset(dwmac->dev, + (void(*)(void *))clk_disable_unprepare, + dwmac->rgmii_tx_clk); + + return 0; +} + static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac) { int ret; @@ -299,16 +315,13 @@ static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac) return ret; } - ret = clk_prepare_enable(dwmac->rgmii_tx_clk); + ret = meson8b_devm_clk_prepare_enable(dwmac, + dwmac->rgmii_tx_clk); if (ret) { dev_err(dwmac->dev, "failed to enable the RGMII TX clock\n"); return ret; } - - devm_add_action_or_reset(dwmac->dev, - (void(*)(void *))clk_disable_unprepare, - dwmac->rgmii_tx_clk); break; case PHY_INTERFACE_MODE_RMII: -- 2.26.2