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Subject: Re: [PATCH v2] ACPI/IORT: Fix PMCG node always look for a single ID
 mapping.
To:     Tuan Phan <tuanphan@os.amperecomputing.com>
CC:     <patches@amperecomputing.com>,
        Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
        Sudeep Holla <sudeep.holla@arm.com>,
        "Rafael J. Wysocki" <rjw@rjwysocki.net>,
        Len Brown <lenb@kernel.org>, <linux-acpi@vger.kernel.org>,
        <linux-arm-kernel@lists.infradead.org>,
        <linux-kernel@vger.kernel.org>
References: <1589327760-5464-1-git-send-email-tuanphan@os.amperecomputing.com>
From:   Hanjun Guo <guohanjun@huawei.com>
Message-ID: <6f9996d3-18f1-0432-0e59-adc2cf086c9c@huawei.com>
Date:   Wed, 13 May 2020 11:16:33 +0800
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On 2020/5/13 7:56, Tuan Phan wrote:
> PMCG node can have zero ID mapping if its overflow interrupt
> is wire based. The code to parse PMCG node can not assume it will
> have a single ID mapping.
> 
> Signed-off-by: Tuan Phan <tuanphan@os.amperecomputing.com>

It's better to add

Fixes: 24e516049360 ("ACPI/IORT: Add support for PMCG")

> ---
> Changes in v2:
> - Used pmcg node to detect wired base overflow interrupt.
>   
>   drivers/acpi/arm64/iort.c | 5 +++++
>   1 file changed, 5 insertions(+)
> 
> diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c
> index ed3d2d1..11a4e8e 100644
> --- a/drivers/acpi/arm64/iort.c
> +++ b/drivers/acpi/arm64/iort.c
> @@ -414,6 +414,7 @@ static struct acpi_iort_node *iort_node_get_id(struct acpi_iort_node *node,
>   static int iort_get_id_mapping_index(struct acpi_iort_node *node)
>   {
>   	struct acpi_iort_smmu_v3 *smmu;
> +	struct acpi_iort_pmcg *pmcg;
>   
>   	switch (node->type) {
>   	case ACPI_IORT_NODE_SMMU_V3:
> @@ -441,6 +442,10 @@ static int iort_get_id_mapping_index(struct acpi_iort_node *node)
>   
>   		return smmu->id_mapping_index;
>   	case ACPI_IORT_NODE_PMCG:
> +		pmcg = (struct acpi_iort_pmcg *)node->node_data;
> +		if (pmcg->overflow_gsiv)
> +			return -EINVAL;
> +
>   		return 0;
>   	default:
>   		return -EINVAL;

With my comments addressed,

Reviewed-by: Hanjun Guo <guoahanjun@huawei.com>