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From:   Thomas Gleixner <tglx@linutronix.de>
To:     Jiaxun Yang <jiaxun.yang@flygoat.com>, maz@kernel.org
Cc:     Jiaxun Yang <jiaxun.yang@flygoat.com>,
        Jason Cooper <jason@lakedaemon.net>,
        Rob Herring <robh+dt@kernel.org>,
        Huacai Chen <chenhc@lemote.com>, linux-kernel@vger.kernel.org,
        devicetree@vger.kernel.org, linux-mips@vger.kernel.org
Subject: Re: [PATCH v2 3/6] irqchip: Add Loongson PCH PIC controller
In-Reply-To: <20200428063247.2223499-3-jiaxun.yang@flygoat.com>
References: <20200422142428.1249684-1-jiaxun.yang@flygoat.com> <20200428063247.2223499-1-jiaxun.yang@flygoat.com> <20200428063247.2223499-3-jiaxun.yang@flygoat.com>
Date:   Wed, 13 May 2020 14:09:09 +0200
Message-ID: <877dxg3ul6.fsf@nanos.tec.linutronix.de>
MIME-Version: 1.0
Content-Type: text/plain
Sender: linux-kernel-owner@vger.kernel.org
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Jiaxun Yang <jiaxun.yang@flygoat.com> writes:
> +static void pch_pic_bitset(struct pch_pic *priv, int offset, int bit)
> +{
> +	void __iomem *addr = priv->base + offset + PIC_REG_IDX(bit) * 4;
> +	unsigned long flags;
> +	u32 reg;
> +
> +	raw_spin_lock_irqsave(&priv->pic_lock, flags);

See other reply.

> +	reg = readl(addr);
> +	reg |= BIT(PIC_REG_BIT(bit));
> +	writel(reg, addr);
> +	raw_spin_unlock_irqrestore(&priv->pic_lock, flags);
> +}
> +static int pch_pic_of_init(struct device_node *node,
> +				struct device_node *parent)
> +{
> +	struct pch_pic *priv;
> +	struct irq_domain *parent_domain;
> +	int err;

ordering

Thanks,

        tglx