Received: by 2002:a25:868d:0:0:0:0:0 with SMTP id z13csp478569ybk; Wed, 13 May 2020 05:15:50 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxsOOC2DIwgdMB5MWj1LKi0jwJNiKBGh0osama0aky7NO1g8+yLNl72HWNJEZJnM8tawf2u X-Received: by 2002:a17:907:94c1:: with SMTP id dn1mr8630895ejc.289.1589372150531; Wed, 13 May 2020 05:15:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1589372150; cv=none; d=google.com; s=arc-20160816; b=Y5NUZblM7qoNvbTxAoxD4ANVahQ9Qbr18+qHPs1DtMWTHyeiK8EdaScglFr6ezW8pU G2lGuEMMu75GRUK6OyJBvOEXIqcI8NG3DcMmHtvJQd2g2WqdvtmGQ7D0UhWTKeUfStqW ztJLi3V4l6jKU8ezMyo21G3KUBKARbVGMbL5LXlR1EF2XWEcMXH3bRgxDJaB+RGRfOPZ 0chHi+8auL8CngwTlvAGIf/efaGpb48LLUwl5aYS+UsRyC77be0YnrJOQbK7d80p/kRq CDjaVhyoltz9u0S3VmC10JeJ0gHgLriXNWJ7pUFDxw04zOtMFUm6I+ajFOaggi5k1nSV ReUA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:message-id:date:references :in-reply-to:subject:cc:to:from; bh=aaxNwJQXNcHwSFyX0exjSGSDVr9lCdO8z/wExWtgO+w=; b=QfTzLREs3lWeBDcm52wQuW2RDIN5youiEBTakkeJ+ZQzswHyfFuPlW+8qQWYea2Vvs 8qSx1Di6GC/z3E4KBbh7Oe+ysKU6Fp6GpTelG2lZYwmWPbxoHVzPB123n5Y9HHOWtJa2 wkA6pMOsBaKe/fwcfCAZG7ouoTeSZ3Agzo51OlGXqQ9BuyiBO5B31gAyZ+SRsgC5mJ37 mi5LGNagB0vcIraSLZvZ8e4Hxm5xVDZXxWqB7/xW0+c5T9KVvycVsNFHP3ie08t2TgWw NeECJF/aWAtrZJRsQ6LXsx+tYH3NGlR9bu3RN5npSdCyPR2CTXu3Bm9VDavZ1/S9wlWU wfuw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id d17si9362124ejh.334.2020.05.13.05.15.26; Wed, 13 May 2020 05:15:50 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731675AbgEMMOC (ORCPT + 99 others); Wed, 13 May 2020 08:14:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43460 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726020AbgEMMOC (ORCPT ); Wed, 13 May 2020 08:14:02 -0400 Received: from Galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A5EA0C061A0C; Wed, 13 May 2020 05:14:01 -0700 (PDT) Received: from p5de0bf0b.dip0.t-ipconnect.de ([93.224.191.11] helo=nanos.tec.linutronix.de) by Galois.linutronix.de with esmtpsa (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1jYqGo-0001x3-GX; Wed, 13 May 2020 14:13:54 +0200 Received: by nanos.tec.linutronix.de (Postfix, from userid 1000) id BBC0F100605; Wed, 13 May 2020 14:13:53 +0200 (CEST) From: Thomas Gleixner To: Jiaxun Yang , maz@kernel.org Cc: Jiaxun Yang , Jason Cooper , Rob Herring , Huacai Chen , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mips@vger.kernel.org Subject: Re: [PATCH v2 5/6] irqchip: Add Loongson PCH MSI controller In-Reply-To: <20200428063247.2223499-5-jiaxun.yang@flygoat.com> References: <20200422142428.1249684-1-jiaxun.yang@flygoat.com> <20200428063247.2223499-1-jiaxun.yang@flygoat.com> <20200428063247.2223499-5-jiaxun.yang@flygoat.com> Date: Wed, 13 May 2020 14:13:53 +0200 Message-ID: <874ksk3uda.fsf@nanos.tec.linutronix.de> MIME-Version: 1.0 Content-Type: text/plain X-Linutronix-Spam-Score: -1.0 X-Linutronix-Spam-Level: - X-Linutronix-Spam-Status: No , -1.0 points, 5.0 required, ALL_TRUSTED=-1,SHORTCIRCUIT=-0.0001 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Jiaxun Yang writes: > + > +struct pch_msi_data { > + spinlock_t msi_map_lock; > + phys_addr_t doorbell; > + u32 irq_first; /* The vector number that MSIs starts */ > + u32 num_irqs; /* The number of vectors for MSIs */ > + unsigned long *msi_map; > +}; > + > +static void pch_msi_mask_msi_irq(struct irq_data *d) > +{ > + pci_msi_mask_irq(d); > + irq_chip_mask_parent(d); > +} > + > +static void pch_msi_unmask_msi_irq(struct irq_data *d) > +{ > + pci_msi_unmask_irq(d); > + irq_chip_unmask_parent(d); The ordering of mask and unmask is assymetric. That does not make sense. > +static struct msi_domain_info pch_msi_domain_info = { > + .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | > + MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX, > + .chip = &pch_msi_irq_chip, Please maintain tabular layout. Thanks, tglx