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From:   Thomas Gleixner <tglx@linutronix.de>
To:     Jiaxun Yang <jiaxun.yang@flygoat.com>, maz@kernel.org
Cc:     Jiaxun Yang <jiaxun.yang@flygoat.com>,
        Jason Cooper <jason@lakedaemon.net>,
        Rob Herring <robh+dt@kernel.org>,
        Huacai Chen <chenhc@lemote.com>, linux-kernel@vger.kernel.org,
        devicetree@vger.kernel.org, linux-mips@vger.kernel.org
Subject: Re: [PATCH v2 5/6] irqchip: Add Loongson PCH MSI controller
In-Reply-To: <874ksk3uda.fsf@nanos.tec.linutronix.de>
References: <20200422142428.1249684-1-jiaxun.yang@flygoat.com> <20200428063247.2223499-1-jiaxun.yang@flygoat.com> <20200428063247.2223499-5-jiaxun.yang@flygoat.com> <874ksk3uda.fsf@nanos.tec.linutronix.de>
Date:   Wed, 13 May 2020 14:15:40 +0200
Message-ID: <871rno3uab.fsf@nanos.tec.linutronix.de>
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Sender: linux-kernel-owner@vger.kernel.org
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Thomas Gleixner <tglx@linutronix.de> writes:
> Jiaxun Yang <jiaxun.yang@flygoat.com> writes:
>> +
>> +struct pch_msi_data {
>> +	spinlock_t		msi_map_lock;
>> +	phys_addr_t		doorbell;
>> +	u32			irq_first;	/* The vector number that MSIs starts */
>> +	u32			num_irqs;	/* The number of vectors for MSIs */
>> +	unsigned long		*msi_map;
>> +};
>> +
>> +static void pch_msi_mask_msi_irq(struct irq_data *d)
>> +{
>> +	pci_msi_mask_irq(d);
>> +	irq_chip_mask_parent(d);
>> +}
>> +
>> +static void pch_msi_unmask_msi_irq(struct irq_data *d)
>> +{
>> +	pci_msi_unmask_irq(d);
>> +	irq_chip_unmask_parent(d);
>
> The ordering of mask and unmask is assymetric. That does not make sense.
>
>> +static struct msi_domain_info pch_msi_domain_info = {
>> +	.flags		= MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
>> +			  MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX,
>> +	.chip	= &pch_msi_irq_chip,
>
> Please maintain tabular layout.

Ooops. Wanted to reply to V3, but the comments are valid for V3 as well.

Thanks,

        tglx