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[23.128.96.18]) by mx.google.com with ESMTP id h10si1732270ejf.487.2020.05.14.06.10.32; Thu, 14 May 2020 06:10:56 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=HQy57Gtt; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726304AbgENNIX (ORCPT + 99 others); Thu, 14 May 2020 09:08:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50922 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1725955AbgENNIR (ORCPT ); Thu, 14 May 2020 09:08:17 -0400 Received: from mail-io1-xd42.google.com (mail-io1-xd42.google.com [IPv6:2607:f8b0:4864:20::d42]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F1112C061A0C; Thu, 14 May 2020 06:08:16 -0700 (PDT) Received: by mail-io1-xd42.google.com with SMTP id o5so1064720iow.8; Thu, 14 May 2020 06:08:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=TxjLQAmlgCmIbW66ttakmR+UHsu55ZGYYjiNgQ7pD60=; b=HQy57GttiwVxh24sQLfeiQngcOiErLC6lrc6A6arkVum1pGd0PXCrQaHvOCK4hPNEV b/059ZwlWVA1AS8FK1q2/gCJIeug5/mReyn6myQQGKj7Nqz7CVRv86DNFSRbqqL9jNJu tITMdAKorHxeF7YvlIBXB8sc7+tzC2Jw9Tf81bsZ6FJbcXdDfUt6nlqKXBjb5tQmn5MB gsR5CUzH/zKAUZsVkX976vv3QKAm1v8PnXFZ2eAaurKTEVbK4xwSxyYq0RD28bfWf5Cm c7yPr6SgCzeFtV1ZHtYdDrrDUR4DC+KkcElHzh4hDhUaeG4VHhyQV+JNQPmJwrKZiy5d Dj2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=TxjLQAmlgCmIbW66ttakmR+UHsu55ZGYYjiNgQ7pD60=; b=uDIITVugJ18J9MzAI1K+7uH1u3m1je5J4rJ+RkFXN/vQGs5ORJGQUAdFRVwL8CvoUo s9W/PI70ZJjjQr+sk9hHXil6NBfoDeOuhRIzULjy5811CxksvyX+qQPt1UI3UffBzwV4 JkoyDMsEIy1/isXnh9zp8w70brsnypgRgsR6tmU+hlBpeCGRGS7Cph9lmNAt6t+J3ZQJ 0BfH8CDTbQtNf6yaLQP0QJRlDC7NxkgvnL6yMlud9w/f7MQOvtukjSfz5B+lRRte3ycS WgZRFzVvlwfUSyHRGIc4RWHgBLS0WGIP8iJP3HooxRQDYXXv8XU1ea48WK86PWVCJXAq E4vQ== X-Gm-Message-State: AOAM533KS1NSUVIvgJ/r7+LxyfLkzvAIGEZ5mnRVXLJv9oYeMQapcr2P jTmstuOgHgN7+KYVy4ztAmw536EefhUULf30/n8= X-Received: by 2002:a5d:8b8e:: with SMTP id p14mr3979084iol.110.1589461696306; Thu, 14 May 2020 06:08:16 -0700 (PDT) MIME-Version: 1.0 References: <1589267017-17294-1-git-send-email-dillon.minfei@gmail.com> <1589267017-17294-4-git-send-email-dillon.minfei@gmail.com> In-Reply-To: From: dillon min Date: Thu, 14 May 2020 21:07:40 +0800 Message-ID: Subject: Re: [PATCH v3 3/5] ARM: dts: stm32: enable ltdc binding with ili9341 on stm32429-disco board To: Alexandre Torgue Cc: Linus Walleij , Rob Herring , Maxime Coquelin , "thierry.reding@gmail.com" , Sam Ravnborg , Dave Airlie , Daniel Vetter , Michael Turquette , Stephen Boyd , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , linux-stm32@st-md-mailman.stormreply.com, Linux ARM , "linux-kernel@vger.kernel.org" , "open list:DRM PANEL DRIVERS" , linux-clk Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Alexandre, On Thu, May 14, 2020 at 8:53 PM Alexandre Torgue wrote: > > > > On 5/14/20 10:24 AM, Linus Walleij wrote: > > On Tue, May 12, 2020 at 9:04 AM wrote: > > > >> From: dillon min > >> > >> Enable the ltdc & ili9341 on stm32429-disco board. > >> > >> Signed-off-by: dillon min > > > > This mostly looks good but... > > > >> +&spi5 { > >> + status = "okay"; > >> + pinctrl-0 = <&spi5_pins>; > >> + pinctrl-names = "default"; > >> + #address-cells = <1>; > >> + #size-cells = <0>; > >> + cs-gpios = <&gpioc 2 GPIO_ACTIVE_LOW>; > >> + dmas = <&dma2 3 2 0x400 0x0>, > >> + <&dma2 4 2 0x400 0x0>; > >> + dma-names = "rx", "tx"; > > > > These DMA assignments seem to be SoC things and should > > rather be in the DTS(I) file where &spi5 is defined, right? > > stm32f429.dtsi I suppose? > > I agree with Linus, DMA have to be defined in SoC dtsi. And if a board > doesn't want to use it, we use the "delete-property". Yes, will move to Soc dtsi in next submits. i'm working on write a v4l2-m2m driver for dma2d of stm32 to support pixel conversion alpha blending between foreground and background graphics. as you know, some soc's engineer trying to add this function to drm system. do you know st's planning about soc's hardware accelerator driver on stm32mp? such as chrom-art, will add to drm subsystem via ioctl to access, or to v4l2, thanks. > > > > > It is likely the same no matter which device is using spi5. > > > > Yours, > > Linus Walleij > >