Received: by 2002:a25:868d:0:0:0:0:0 with SMTP id z13csp2139790ybk; Sun, 17 May 2020 11:27:03 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxWrwf/qrUQ0Xp+tL7/WTPp1jiFc8v8JjRw1tSrpLvaHuOIIJE/Qpql4tCm19pJQdhrdhzC X-Received: by 2002:a50:e04c:: with SMTP id g12mr11009560edl.74.1589740023329; Sun, 17 May 2020 11:27:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1589740023; cv=none; d=google.com; s=arc-20160816; b=iwwrluyInqJB0RGJhafpHdC0VmJbj14v0RpnsMzK+jXClYk0/LMGI4/vmH0JPouJEX ejGXbnFY5ZJKWJ3YH62yzJvBs5WTQ2tl2LCyXqu/mGZP8O62fKfgurC5NR+pp1XaVL6k GZU2JiHJouuZYbXW5PBQp+uhm3+GiXQKoJh2/QyjJ1NFjVdWNZJz/+3uSsut8+71J2qK 2SVnAkUi8AmjRPZhMjps7kHHShsYQgH/4tV2e25HQJJvHDQ3UnyzxpLbhWjl/2CNndK0 Z9YQoxYAmj3G8XKQmQiHsct9MHfY/kw7n23p3sRXxAof1fI2gjq7G26J85vWNbQ4Gzzy dJAg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:in-reply-to:content-disposition :mime-version:references:message-id:subject:cc:to:from:date; bh=fGRVqfhybg+d5gCE7nRnawGRYz1WsoUf+J9pDUL7qEU=; b=G4cBCZX+6bmQxzeFaeyzSXEJuJSG7W15h6i7+K3QpwnAH0LjcoOoVUys0oSsGOM+tz 8FSz5oFzTBwQRpvUJtf+swUQicDlY45PcMIJxIwkY52iuc3dAK7CH17KmcvI0v+ZjTOt 1n1Gl2PUNFV4KyHpp6WS9Z/bAlvy2mnq1Au8pr6O56HRsEdpIFIzBPD7/aAv5EMBAFiG xulak4REI81F/tMF1htfVgp2QGFkMMsDMmDmI/l0y+70bx3rnIsaALmwWrwurtYS0/3o dydUQthM+j1N5KLYofRANiHMTT8FPz3LCGtHx8tXh/YW/2DyYDxgGPO08eBX6+JdHBp+ Z/Gg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id e1si3490878edv.420.2020.05.17.11.26.38; Sun, 17 May 2020 11:27:03 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726299AbgEQSWQ (ORCPT + 99 others); Sun, 17 May 2020 14:22:16 -0400 Received: from mail.baikalelectronics.com ([87.245.175.226]:42716 "EHLO mail.baikalelectronics.ru" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726259AbgEQSWP (ORCPT ); Sun, 17 May 2020 14:22:15 -0400 Received: from localhost (unknown [127.0.0.1]) by mail.baikalelectronics.ru (Postfix) with ESMTP id 03DFB8030802; Sun, 17 May 2020 18:22:12 +0000 (UTC) X-Virus-Scanned: amavisd-new at baikalelectronics.ru Received: from mail.baikalelectronics.ru ([127.0.0.1]) by localhost (mail.baikalelectronics.ru [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id xlnnS2shJqbh; Sun, 17 May 2020 21:22:11 +0300 (MSK) Date: Sun, 17 May 2020 21:22:10 +0300 From: Serge Semin To: Andy Shevchenko CC: Serge Semin , Vinod Koul , Vineet Gupta , Viresh Kumar , Dan Williams , Alexey Malahov , Thomas Bogendoerfer , Paul Burton , Ralf Baechle , Arnd Bergmann , Rob Herring , , , , Subject: Re: [PATCH v2 3/6] dmaengine: dw: Set DMA device max segment size parameter Message-ID: <20200517182210.jxtsqbtf3pjogxpc@mobilestation> References: <20200306131048.ADBE18030797@mail.baikalelectronics.ru> <20200508105304.14065-1-Sergey.Semin@baikalelectronics.ru> <20200508105304.14065-4-Sergey.Semin@baikalelectronics.ru> <20200508112152.GI185537@smile.fi.intel.com> <20200511211622.yuh3ls2ay76yaxrf@mobilestation> <20200512123551.GX185537@smile.fi.intel.com> <20200515061601.GG333670@vkoul-mobl> <20200515105313.GL185537@smile.fi.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20200515105313.GL185537@smile.fi.intel.com> X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, May 15, 2020 at 01:53:13PM +0300, Andy Shevchenko wrote: > On Fri, May 15, 2020 at 11:46:01AM +0530, Vinod Koul wrote: > > On 12-05-20, 15:35, Andy Shevchenko wrote: > > > On Tue, May 12, 2020 at 12:16:22AM +0300, Serge Semin wrote: > > > > On Fri, May 08, 2020 at 02:21:52PM +0300, Andy Shevchenko wrote: > > > > > On Fri, May 08, 2020 at 01:53:01PM +0300, Serge Semin wrote: > > ... > > > > My point here that we probably can avoid complications till we have real > > > hardware where it's different. As I said I don't remember a such, except > > > *maybe* Intel Medfield, which is quite outdated and not supported for wider > > > audience anyway. > > > > IIRC Intel Medfield has couple of dma controller instances each one with > > different parameters *but* each instance has same channel configuration. > > That's my memory too. > > > I do not recall seeing that we have synthesis parameters per channel > > basis... But I maybe wrong, it's been a while. > > Exactly, that's why I think we better simplify things till we will have real > issue with it. I.o.w. no need to solve the problem which doesn't exist. Ok then. My hardware is also synthesized with uniform max block size parameter. I'll remove that maximum of maximum search pattern and use the block size found for the very first channel to set the maximum segment size parameter. -Sergey > > -- > With Best Regards, > Andy Shevchenko > >