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[23.128.96.18]) by mx.google.com with ESMTP id oy14si4022338ejb.358.2020.05.17.23.38.18; Sun, 17 May 2020 23:38:42 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=G3b7ywlj; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726732AbgERFqe (ORCPT + 99 others); Mon, 18 May 2020 01:46:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60562 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726040AbgERFqd (ORCPT ); Mon, 18 May 2020 01:46:33 -0400 Received: from mail-lf1-x142.google.com (mail-lf1-x142.google.com [IPv6:2a00:1450:4864:20::142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4FCF9C061A0C for ; Sun, 17 May 2020 22:46:33 -0700 (PDT) Received: by mail-lf1-x142.google.com with SMTP id h26so6912489lfg.6 for ; Sun, 17 May 2020 22:46:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=ygsoJcQzy2g2jI/Taob7j4UIGHvK7ly0RJpFdbU+Cb4=; b=G3b7ywljZcZCAX7nJXBHWye89fgIXWV1Y/Zi9/UIsGwtIZiAQx6o0HUfhuMVoDPo1w hLvGWKlDX+XuIqbe3zySiJ9YKptYVBEz7TNH6oKzYopJNoJY37POYt3GcdMgO8U647BS sEBMh9Qv3TmZ7Mps0cLu+9qi/HJniKyoE5IT/B1tEfEs9oKHXXAwf2KIN+WWwJwUQyRZ KCZakvpO8oHau4eSIUGwLM09uWOlVosi5UtGk/WAqYqOlqII3hyHZRvOFDzXPNdNX+nd UoEdzxlsRe9mhcxNjNtn81gNC8rPkwKMYMiPW5cMIMMQ2wdPlVYVDDZ+R7OvN0P2uE7f hqYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=ygsoJcQzy2g2jI/Taob7j4UIGHvK7ly0RJpFdbU+Cb4=; b=l7lIPZ0mWoh6U156raOzyn6AteJxW8bn7zZJSJosdH7sPQnCsW4vL5Ad8u6UQB1Etm TUUJRQPkp3zTsIRCW+COSxjSXIjkWzPFBRdCsxaDy61YNnmzPHIYHqr5JtWEl7KYSMCv 3EUfNI4da8F/zpUrwYC/R8xxaJ3AbNme5x0zgrcj+EyJe+GaG6n1fsIWufT7oeVrlC+U HwYHp+hvEDgJhxfWPffAd+pHgyT4MK69bl5v2/Ny6ffksjEvcoQPmoaeIhqqK1TMVSzy mJrLi+/5n+JRKXgvIe9nAIKRijXW/189PYAqLxg1onXtgGI4tNVNzLeZXXp+QLMHOsPV bZlA== X-Gm-Message-State: AOAM531uetNv12+szXNW+CPKk7sc6gQ9kSq6SH5IojSykMpi6CeQGAO3 rVnYP5Wt/8GZqCorOz6k2F11gAc8RSO5aHTiFgoAXw== X-Received: by 2002:ac2:4293:: with SMTP id m19mr10444777lfh.204.1589780791774; Sun, 17 May 2020 22:46:31 -0700 (PDT) MIME-Version: 1.0 References: <20200516124857.75004-1-lecopzer@gmail.com> In-Reply-To: <20200516124857.75004-1-lecopzer@gmail.com> From: Sumit Garg Date: Mon, 18 May 2020 11:16:20 +0530 Message-ID: Subject: Re: [PATCH 0/3] arm64: perf: Add support for Perf NMI interrupts To: Lecopzer Chen , julien.thierry.kdev@gmail.com Cc: Linux Kernel Mailing List , Mark Rutland , lecopzer.chen@mediatek.com, alexander.shishkin@linux.intel.com, Catalin Marinas , jolsa@redhat.com, acme@kernel.org, Peter Zijlstra , mingo@redhat.com, linux-mediatek@lists.infradead.org, matthias.bgg@gmail.com, namhyung@kernel.org, Will Deacon , yj.chiang@mediatek.com, linux-arm-kernel Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org + Julien Hi Lecopzer, On Sat, 16 May 2020 at 18:20, Lecopzer Chen wrote: > > These series implement Perf NMI funxtionality and depends on > Pseudo NMI [1] which has been upstreamed. > > In arm64 with GICv3, Pseudo NMI was implemented for NMI-like interruts. > That can be extended to Perf NMI which is the prerequisite for hard-lockup > detector which had already a standard interface inside Linux. > > Thus the first step we need to implement perf NMI interface and make sure > it works fine. > This is something that is already implemented via Julien's patch-set [1]. Its v4 has been floating since July, 2019 and I couldn't find any major blocking comments but not sure why things haven't progressed further. Maybe Julien or Arm maintainers can provide updates on existing patch-set [1] and how we should proceed further with this interesting feature. And regarding hard-lockup detection, I have been able to enable it based on perf NMI events using Julien's perf patch-set [1]. Have a look at the patch here [2]. [1] https://patchwork.kernel.org/cover/11047407/ [2] http://lists.infradead.org/pipermail/linux-arm-kernel/2020-May/732227.html -Sumit > Perf NMI has been test by dd if=/dev/urandom of=/dev/null like the link [2] > did. > > [1] https://lkml.org/lkml/2019/1/31/535 > [2] https://www.linaro.org/blog/debugging-arm-kernels-using-nmifiq > > > Lecopzer Chen (3): > arm_pmu: Add support for perf NMI interrupts registration > arm64: perf: Support NMI context for perf event ISR > arm64: Kconfig: Add support for the Perf NMI > > arch/arm64/Kconfig | 10 +++++++ > arch/arm64/kernel/perf_event.c | 36 ++++++++++++++++++------ > drivers/perf/arm_pmu.c | 51 ++++++++++++++++++++++++++++++---- > include/linux/perf/arm_pmu.h | 6 ++++ > 4 files changed, 88 insertions(+), 15 deletions(-) > > -- > 2.25.1 > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel