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Mon, 18 May 2020 09:15:20 +0000 From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Jason Cooper , Marc Zyngier Cc: Atish Patra , Alistair Francis , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel , stable@vger.kernel.org Subject: [PATCH v2 2/3] irqchip/sifive-plic: Setup cpuhp once after boot CPU handler is present Date: Mon, 18 May 2020 14:44:40 +0530 Message-Id: <20200518091441.94843-3-anup.patel@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200518091441.94843-1-anup.patel@wdc.com> References: <20200518091441.94843-1-anup.patel@wdc.com> Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: MA1PR01CA0155.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:71::25) To DM6PR04MB6201.namprd04.prod.outlook.com (2603:10b6:5:127::32) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from wdc.com (106.51.27.1) by MA1PR01CA0155.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:71::25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3000.25 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: WW9oqxWgNXD9GyCHDd5yCZ4o9ToDfz1a6XCe3aQPXEOG4A0B39qIeHlU3oIlJG3UiYwv9vO4SoMSKfN6+wTWW9hLbhA3m8aKx9/8qhrpuwTiBU/r1v5zJeIfV0Qqeo4t68gso/fDiq03kM4j7EMJeBOilwD16LoCf72PFi5y/hQ5Yy9V0RJB6cUINZtHv0b8aYsHjHA0IG4YUh+/R3MdxC8bRYUutrd0fhhYvmYKuFoStvzAQKHsR96yhujNHj/ikFaRFRKuJcQHoFa63nFw992PXF7YtILfV4/g4h+ZuTHj63BcqGVoe3q7MIqGVkAzoyFNmq5PgZIXBVuzutUQb/dcfXQWwhEuQ176d4zfa9AqqZsYAwnEE6YXMPc/PR9CtEe6sdGrPoaPmG7oq1yAZhKTtO26CPiit8Mya7CxJvO2FCzJuFwk3LBiBTTrsUWK1olHwb58w5ovzDIQAO2h8aufwmVGfMuUWqGhYl7viSc= X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: d018a8c0-1397-4ba6-7330-08d7fb0bfd04 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 May 2020 09:15:20.5812 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 1JKt9zhW7gqu4eF2HIvegT/l/tt1RsD35DkrOubvLBI8EXfAdx7f7ZYv8FvmWwMKyt+0nOv3hRMBn8txUCPVKA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR04MB4155 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org For multiple PLIC instances, the plic_init() is called once for each PLIC instance. Due to this we have two issues: 1. cpuhp_setup_state() is called multiple times 2. plic_starting_cpu() can crash for boot CPU if cpuhp_setup_state() is called before boot CPU PLIC handler is available. This patch fixes both above issues. Fixes: f1ad1133b18f ("irqchip/sifive-plic: Add support for multiple PLICs") Cc: stable@vger.kernel.org Signed-off-by: Anup Patel --- drivers/irqchip/irq-sifive-plic.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c index 9f7f8ce88c00..6c54abf5cc5e 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -76,6 +76,7 @@ struct plic_handler { void __iomem *enable_base; struct plic_priv *priv; }; +static bool plic_cpuhp_setup_done; static DEFINE_PER_CPU(struct plic_handler, plic_handlers); static inline void plic_toggle(struct plic_handler *handler, @@ -285,6 +286,7 @@ static int __init plic_init(struct device_node *node, int error = 0, nr_contexts, nr_handlers = 0, i; u32 nr_irqs; struct plic_priv *priv; + struct plic_handler *handler; priv = kzalloc(sizeof(*priv), GFP_KERNEL); if (!priv) @@ -313,7 +315,6 @@ static int __init plic_init(struct device_node *node, for (i = 0; i < nr_contexts; i++) { struct of_phandle_args parent; - struct plic_handler *handler; irq_hw_number_t hwirq; int cpu, hartid; @@ -367,9 +368,18 @@ static int __init plic_init(struct device_node *node, nr_handlers++; } - cpuhp_setup_state(CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING, + /* + * We can have multiple PLIC instances so setup cpuhp state only + * when context handler for current/boot CPU is present. + */ + handler = this_cpu_ptr(&plic_handlers); + if (handler->present && !plic_cpuhp_setup_done) { + cpuhp_setup_state(CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING, "irqchip/sifive/plic:starting", plic_starting_cpu, plic_dying_cpu); + plic_cpuhp_setup_done = true; + } + pr_info("mapped %d interrupts with %d handlers for %d contexts.\n", nr_irqs, nr_handlers, nr_contexts); set_handle_irq(plic_handle_irq); -- 2.25.1