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Date:   Mon, 18 May 2020 11:23:18 +0200
From:   Peter Zijlstra <peterz@infradead.org>
To:     Stephane Eranian <eranian@google.com>
Cc:     linux-kernel@vger.kernel.org, mingo@elte.hu, irogers@google.com,
        kim.phillips@amd.com, jolsa@redhat.com
Subject: Re: [PATCH 2/3] perf/x86/rapl: refactor code for Intel/AMD sharing
Message-ID: <20200518092318.GA277222@hirez.programming.kicks-ass.net>
References: <20200515215733.20647-1-eranian@google.com>
 <20200515215733.20647-3-eranian@google.com>
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On Fri, May 15, 2020 at 02:57:32PM -0700, Stephane Eranian wrote:
> This patch modifies the rapl_model struct to include architecture specific
> knowledge to Intel specific structure, and in particular the MSR for
> POWER_UNIT and the rapl_msrs array.
> 
> No functional changes.
> 
> Signed-off-by: Stephane Eranian <eranian@google.com>
> ---
>  arch/x86/events/rapl.c | 29 +++++++++++++++++++++++------
>  1 file changed, 23 insertions(+), 6 deletions(-)
> 
> diff --git a/arch/x86/events/rapl.c b/arch/x86/events/rapl.c
> index ece043fb7b494..e98f627a13fa8 100644
> --- a/arch/x86/events/rapl.c
> +++ b/arch/x86/events/rapl.c
> @@ -131,7 +131,9 @@ struct rapl_pmus {
>  };
>  
>  struct rapl_model {
> +	struct perf_msr *rapl_msrs;
>  	unsigned long	events;
> +	int		msr_power_unit;

MSR addresses go negative these days?