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[23.128.96.18]) by mx.google.com with ESMTP id k13si6397002edn.344.2020.05.18.07.22.29; Mon, 18 May 2020 07:22:55 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727942AbgEROT5 (ORCPT + 99 others); Mon, 18 May 2020 10:19:57 -0400 Received: from foss.arm.com ([217.140.110.172]:41548 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726918AbgEROT5 (ORCPT ); Mon, 18 May 2020 10:19:57 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6E3C2101E; Mon, 18 May 2020 07:19:56 -0700 (PDT) Received: from C02TD0UTHF1T.local (unknown [10.57.29.34]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B7F9E3F52E; Mon, 18 May 2020 07:19:52 -0700 (PDT) Date: Mon, 18 May 2020 15:19:46 +0100 From: Mark Rutland To: Sumit Garg Cc: Alexandru Elisei , Lecopzer Chen , julien.thierry.kdev@gmail.com, Linux Kernel Mailing List , Jian-Lin Chen , alexander.shishkin@linux.intel.com, Catalin Marinas , jolsa@redhat.com, acme@kernel.org, Peter Zijlstra , mingo@redhat.com, linux-mediatek@lists.infradead.org, matthias.bgg@gmail.com, namhyung@kernel.org, Will Deacon , yj.chiang@mediatek.com, linux-arm-kernel Subject: Re: [PATCH 0/3] arm64: perf: Add support for Perf NMI interrupts Message-ID: <20200518141946.GA3164@C02TD0UTHF1T.local> References: <20200516124857.75004-1-lecopzer@gmail.com> <20200518104524.GA1224@C02TD0UTHF1T.local> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, May 18, 2020 at 07:39:23PM +0530, Sumit Garg wrote: > On Mon, 18 May 2020 at 16:47, Alexandru Elisei wrote: > > On 5/18/20 11:45 AM, Mark Rutland wrote: > > > On Mon, May 18, 2020 at 02:26:00PM +0800, Lecopzer Chen wrote: > > >> HI Sumit, > > >> > > >> Thanks for your information. > > >> > > >> I've already implemented IPI (same as you did [1], little difference > > >> in detail), hardlockup detector and perf in last year(2019) for > > >> debuggability. > > >> And now we tend to upstream to reduce kernel maintaining effort. > > >> I'm glad if someone in ARM can do this work :) > > >> > > >> Hi Julien, > > >> > > >> Does any Arm maintainers can proceed this action? > > > Alexandru (Cc'd) has been rebasing and reworking Julien's patches, which > > > is my preferred approach. > > > > > > I understand that's not quite ready for posting since he's investigating > > > some of the nastier subtleties (e.g. mutual exclusion with the NMI), but > > > maybe we can put the work-in-progress patches somewhere in the mean > > > time. > > > > > > Alexandru, do you have an idea of what needs to be done, and/or when you > > > expect you could post that? > > > > I'm currently working on rebasing the patches on top of 5.7-rc5, when I have > > something usable I'll post a link (should be a couple of days). After that I will > > address the review comments, and I plan to do a thorough testing because I'm not > > 100% confident that some of the assumptions around the locks that were removed are > > correct. My guess is this will take a few weeks. > > > > Thanks Mark, Alex for the status updates on perf NMI feature. > > Alex, > > As the hard-lockup detection patch [1] has a dependency on perf NMI > patch-set, I will rebase and test hard-lockup detector when you have > got a working tree. But due to the dependency, I think patch [1] > should be accepted along with perf NMI patch-set. So would you be open > to include this patch as part of your series? > > [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2020-May/732227.html While it depends on the perf NMI bits, I don't think it makes sense to tie that into the series given it's trying to achieve something very different. I think that should be reposted separately once the perf NMI bits are in shape. Thanks, Mark.