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From:   Baolin Wang <baolin.wang7@gmail.com>
Date:   Tue, 19 May 2020 21:12:22 +0800
Message-ID: <CADBw62oewy=9GK3jet4Y2=JmHqBMmDQ7XMADD8uOiiwxHOEGbg@mail.gmail.com>
Subject: Re: [PATCH 1/2] clk: sprd: mark the local clock symbols static
To:     Chunyan Zhang <zhang.lyra@gmail.com>
Cc:     Stephen Boyd <sboyd@kernel.org>,
        Michael Turquette <mturquette@baylibre.com>,
        linux-clk@vger.kernel.org, LKML <linux-kernel@vger.kernel.org>,
        Orson Zhai <orsonzhai@gmail.com>,
        Chunyan Zhang <chunyan.zhang@unisoc.com>
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On Tue, May 19, 2020 at 11:00 AM Chunyan Zhang <zhang.lyra@gmail.com> wrote:
>
> From: Chunyan Zhang <chunyan.zhang@unisoc.com>
>
> There's a few pll gate clocks which were not marked with static, and
> those clock are used only in the current file, so add static key word
> for them.
>
> Fixes: 0e4b8a2349f3 ("clk: sprd: add clocks support for SC9863A")
> Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com>

Reviewed-by: Baolin Wang <baolin.wang7@gmail.com>

> ---
>  drivers/clk/sprd/sc9863a-clk.c | 32 ++++++++++++++++----------------
>  1 file changed, 16 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/clk/sprd/sc9863a-clk.c b/drivers/clk/sprd/sc9863a-clk.c
> index 9568ec956ee4..ad2e0f9f8563 100644
> --- a/drivers/clk/sprd/sc9863a-clk.c
> +++ b/drivers/clk/sprd/sc9863a-clk.c
> @@ -23,22 +23,22 @@
>  #include "pll.h"
>
>  /* mpll*_gate clocks control cpu cores, they were enabled by default */
> -SPRD_PLL_SC_GATE_CLK_FW_NAME(mpll0_gate, "mpll0-gate", "ext-26m", 0x94,
> -                            0x1000, BIT(0), CLK_IGNORE_UNUSED, 0, 240);
> -SPRD_PLL_SC_GATE_CLK_FW_NAME(dpll0_gate, "dpll0-gate", "ext-26m", 0x98,
> -                            0x1000, BIT(0), 0, 0, 240);
> -SPRD_PLL_SC_GATE_CLK_FW_NAME(lpll_gate, "lpll-gate", "ext-26m", 0x9c,
> -                            0x1000, BIT(0), 0, 0, 240);
> -SPRD_PLL_SC_GATE_CLK_FW_NAME(gpll_gate, "gpll-gate", "ext-26m", 0xa8,
> -                            0x1000, BIT(0), 0, 0, 240);
> -SPRD_PLL_SC_GATE_CLK_FW_NAME(dpll1_gate, "dpll1-gate", "ext-26m", 0x1dc,
> -                            0x1000, BIT(0), 0, 0, 240);
> -SPRD_PLL_SC_GATE_CLK_FW_NAME(mpll1_gate, "mpll1-gate", "ext-26m", 0x1e0,
> -                            0x1000, BIT(0), CLK_IGNORE_UNUSED, 0, 240);
> -SPRD_PLL_SC_GATE_CLK_FW_NAME(mpll2_gate, "mpll2-gate", "ext-26m", 0x1e4,
> -                            0x1000, BIT(0), CLK_IGNORE_UNUSED, 0, 240);
> -SPRD_PLL_SC_GATE_CLK_FW_NAME(isppll_gate, "isppll-gate", "ext-26m", 0x1e8,
> -                            0x1000, BIT(0), 0, 0, 240);
> +static SPRD_PLL_SC_GATE_CLK_FW_NAME(mpll0_gate, "mpll0-gate", "ext-26m", 0x94,
> +                                   0x1000, BIT(0), CLK_IGNORE_UNUSED, 0, 240);
> +static SPRD_PLL_SC_GATE_CLK_FW_NAME(dpll0_gate, "dpll0-gate", "ext-26m", 0x98,
> +                                   0x1000, BIT(0), 0, 0, 240);
> +static SPRD_PLL_SC_GATE_CLK_FW_NAME(lpll_gate, "lpll-gate", "ext-26m", 0x9c,
> +                                   0x1000, BIT(0), 0, 0, 240);
> +static SPRD_PLL_SC_GATE_CLK_FW_NAME(gpll_gate, "gpll-gate", "ext-26m", 0xa8,
> +                                   0x1000, BIT(0), 0, 0, 240);
> +static SPRD_PLL_SC_GATE_CLK_FW_NAME(dpll1_gate, "dpll1-gate", "ext-26m", 0x1dc,
> +                                   0x1000, BIT(0), 0, 0, 240);
> +static SPRD_PLL_SC_GATE_CLK_FW_NAME(mpll1_gate, "mpll1-gate", "ext-26m", 0x1e0,
> +                                   0x1000, BIT(0), CLK_IGNORE_UNUSED, 0, 240);
> +static SPRD_PLL_SC_GATE_CLK_FW_NAME(mpll2_gate, "mpll2-gate", "ext-26m", 0x1e4,
> +                                   0x1000, BIT(0), CLK_IGNORE_UNUSED, 0, 240);
> +static SPRD_PLL_SC_GATE_CLK_FW_NAME(isppll_gate, "isppll-gate", "ext-26m",
> +                                   0x1e8, 0x1000, BIT(0), 0, 0, 240);
>
>  static struct sprd_clk_common *sc9863a_pmu_gate_clks[] = {
>         /* address base is 0x402b0000 */
> --
> 2.20.1
>


-- 
Baolin Wang