Received: by 2002:a25:868d:0:0:0:0:0 with SMTP id z13csp3674072ybk; Tue, 19 May 2020 10:13:25 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyUGgd9OHGP3jl390Z4ST+X54ZfxKOXW2voMyFZ6iv1E+NKrk/0jem0ltvB+zWIR/pN+fzq X-Received: by 2002:a17:906:379a:: with SMTP id n26mr181970ejc.513.1589908405047; Tue, 19 May 2020 10:13:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1589908405; cv=none; d=google.com; s=arc-20160816; b=BhFzitg1mLmroVx6ppo92X7x7tiA8k4VKQg+K7eIpBfHVlSTnbWrTJbMs1gu0S5Txm NRi0Zx242S8hHPNBN+h3MqG5iLf6Gy3AWgQzcHYQEc2OmQDk+mn75SdUFwmJmB2wZQTc e+Er7IeqD6S07n3TmiUSeYW1yzq15Lk5m4/tHaCz0cQfeakNw+eSUOCVePPEnTo6KEA8 s4xje6m5G+hidVVKlv2nMXWcVCHSG9piAK40vCocIllLTcvNexgrWOVpiGxuIH2wWV+C WQmB7Oq7gX+bAOMHwAG22oMXg959gIBvlrWS2dnmMJIT2GdrXuXgXRJ37XItah29Z5XI YUnw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:user-agent:message-id:date:subject:cc:to :from; bh=RIhMI5Uoek9osZxGAoguBg8N0C8jbiHbFlcMEfs2jJw=; b=citk/J7wZPo09Fa/Sgk9nXLmmax7VZNQcYj/XcpUUfqv1wZj+X37yOIs9E2pNq490c 5kFIlhij/b9lDy+bhUSIvg6b7Jibzybn3AVicWFbj+Z86z6JxMDE29YPQLHWGwnJrZBN lNkT57Ewx5c4Z7b3XBMYuuHsqoDCl6iNdoBzexrl0MW4Q67k8LIiJvuaCtCoIc2CxS2A prgLZ5ZwZ+YITh9svDV35jh6K1m7FYnj/vxFtblu8dEMBVFi9AAziW/rRqyHFWUOKA0L TaWUZZ1D+Ar/WZaw+GSNiiVbMYN7o0aHc5LsfSDrbNTccWiq7yt2HohtAWeH6+xmoopu FwLw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id t10si16917edw.408.2020.05.19.10.13.00; Tue, 19 May 2020 10:13:25 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729407AbgESRLB (ORCPT + 99 others); Tue, 19 May 2020 13:11:01 -0400 Received: from mailrelay4.webfaction.com ([185.20.51.6]:57804 "EHLO mailrelay4.webfaction.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729001AbgESRLB (ORCPT ); Tue, 19 May 2020 13:11:01 -0400 Received: from mailrelay3.webfaction.com (mailrelay3.webfaction.com [207.38.93.110]) by mailrelay4.webfaction.com (Postfix) with ESMTPS id AA711A6D79; Tue, 19 May 2020 17:10:54 +0000 (UTC) Received: from mailrelay1.webfaction.com (mailrelay1.webfaction.com [207.38.86.46]) by mailrelay3.webfaction.com (Postfix) with ESMTPS id DEEE32A5088; Tue, 19 May 2020 17:10:52 +0000 (UTC) Received: from smtp.webfaction.com (mail6.webfaction.com [31.170.123.134]) by mailrelay1.webfaction.com (Postfix) with ESMTPS id EA76E1A0E3D; Tue, 19 May 2020 17:10:51 +0000 (UTC) Received: from jeremy.localnet (host-37-191-188-128.lynet.no [37.191.188.128]) by smtp.webfaction.com (Postfix) with ESMTPSA id 810DA60038E8E; Tue, 19 May 2020 17:11:01 +0000 (UTC) From: Paul Boddie To: dri-devel@lists.freedesktop.org Cc: Paul Cercueil , Emil Velikov , devicetree , od@zcrc.me, "Rafael J . Wysocki" , David Airlie , Greg Kroah-Hartman , linux-kernel@vger.kernel.org, Rob Herring Subject: Re: [PATCH 11/12] gpu/drm: Ingenic: Add support for the IPU Date: Tue, 19 May 2020 19:10:32 +0200 Message-ID: <3220152.ycyENPvHUQ@jeremy> User-Agent: KMail/4.14.1 (Linux/3.16.0-10-586; KDE/4.14.2; i686; ; ) In-Reply-To: References: <20200516215057.392609-1-paul@crapouillou.net> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Monday 18. May 2020 13.26.58 Paul Cercueil wrote: > >> > >> @@ -186,13 +186,16 @@ static void > >> > >> ingenic_drm_crtc_update_timings(struct ingenic_drm *priv, > >> > >> regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, > >> JZ_LCD_CTRL_OFUP | JZ_LCD_CTRL_BURST_16, > >> JZ_LCD_CTRL_OFUP | JZ_LCD_CTRL_BURST_16); > >> > >> + > >> + regmap_write(priv->map, JZ_REG_LCD_IPUR, JZ_LCD_IPUR_IPUREN > >> + (ht * vpe / 3) << JZ_LCD_IPUR_IPUR_LSB); > > > > This hunk also indicates that it may be better to merge the IPU within > > the existing driver. > > This writes the IPUR register of the CRTC, nothing wrong here. Since I noticed it in the above patch details, I think the mask when updating the burst setting in the LCD_CTRL register should - in general - involve multiple bits, since the BST field is 3 bits wide on the JZ4780 and 2 bits wide on earlier products. Just setting BURST_16 (0b10) could potentially enable BURST_32 (0b11) or other field values that are not explicitly defined. Hope this is useful! Paul