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[23.128.96.18]) by mx.google.com with ESMTP id a3si188985eds.355.2020.05.19.12.11.03; Tue, 19 May 2020 12:11:28 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@nvidia.com header.s=n1 header.b=qvZKjOCi; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726957AbgESTHc (ORCPT + 99 others); Tue, 19 May 2020 15:07:32 -0400 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:3409 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726059AbgESTHb (ORCPT ); Tue, 19 May 2020 15:07:31 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 19 May 2020 12:07:19 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 19 May 2020 12:07:31 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 19 May 2020 12:07:31 -0700 Received: from [10.2.164.184] (172.20.13.39) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 19 May 2020 19:07:30 +0000 Subject: Re: [PATCH v1] sdhci: tegra: Remove warnings about missing device-tree properties From: Sowjanya Komatineni To: Dmitry Osipenko , Thierry Reding CC: Ulf Hansson , Jonathan Hunter , Adrian Hunter , "linux-mmc@vger.kernel.org" , linux-tegra , Linux Kernel Mailing List References: <20200516154314.14769-1-digetx@gmail.com> <20200519162444.GD2113674@ulmo> <11c93dac-f5ba-2193-6f44-63af27fdce09@nvidia.com> Message-ID: Date: Tue, 19 May 2020 12:07:28 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.7.0 MIME-Version: 1.0 In-Reply-To: X-Originating-IP: [172.20.13.39] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: quoted-printable Content-Language: en-US DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1589915239; bh=s6uam05ArM6BiI5b00L7hD1ybeok2Wgo9Vnh25tsBjM=; h=X-PGP-Universal:Subject:From:To:CC:References:Message-ID:Date: User-Agent:MIME-Version:In-Reply-To:X-Originating-IP: X-ClientProxiedBy:Content-Type:Content-Transfer-Encoding: Content-Language; b=qvZKjOCiZVe0c1lxZxtvzU8OQFU8m9bPfOb325PbIRH/WOZxSygAS61Rw23ZCM2Uk f2O4vgzWe5Dt82fS2qx6+DmV+jHKxd9IkMf75U2eXOKLE6+Kiy8fwHhJZrMu328LmN h508L3CC0IS4KmCFV1rD/stVZTyfNeafTa7mJXUy5U0U8jQNVuPhV5UoAQKRqOOv1f /yIH4QVNzI+7CnZy9WlGIZ8doptV/Qfyo6ZKaR4gNGudqhw/Hfa5Kx0uUHnmAmhYV4 ysirI+fHK3Kuo/ESILzbxBTqeRoptlEghRLOec8ulWdMg1WYT+HJOX9aKx5D/UL91c T2o/jte13E0tQ== Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 5/19/20 11:41 AM, Sowjanya Komatineni wrote: > > On 5/19/20 11:34 AM, Sowjanya Komatineni wrote: >> >> On 5/19/20 9:33 AM, Dmitry Osipenko wrote: >>> 19.05.2020 19:24, Thierry Reding =D0=BF=D0=B8=D1=88=D0=B5=D1=82: >>>> On Tue, May 19, 2020 at 05:05:27PM +0300, Dmitry Osipenko wrote: >>>>> 19.05.2020 10:28, Ulf Hansson =D0=BF=D0=B8=D1=88=D0=B5=D1=82: >>>>>> On Sat, 16 May 2020 at 17:44, Dmitry Osipenko =20 >>>>>> wrote: >>>>>>> Several people asked me about the MMC warnings in the KMSG log and >>>>>>> I had to tell to ignore them because these warning are=20 >>>>>>> irrelevant to >>>>>>> pre-Tegra210 SoCs. >>>>>> Why are the warnings irrelevant? >>>>> That's what the DT binding doc says [1]. >>>>> >>>>> [1] >>>>> https://www.kernel.org/doc/Documentation/devicetree/bindings/mmc/nvid= ia%2Ctegra20-sdhci.txt=20 >>>>> >>>>> >>>>> Although, looking at the driver's code and TRM docs, it seems that=20 >>>>> all >>>>> those properties are really irrelevant only to the older Terga20=20 >>>>> SoC. So >>>>> the binding doc is a bit misleading. >>>>> >>>>> Nevertheless, the binding explicitly says that the properties are >>>>> optional, which is correct. >>>> Optional only means that drivers must not fail if these properties >>>> aren't found, it doesn't mean that the driver can't warn that they >>>> are missing. >>>> >>>> Quite possibly the only reason why they were made optional is because >>>> they weren't part of the bindings since the beginning. Anything added >>>> to a binding after the first public release has to be optional by >>>> definition, otherwise DT ABI wouldn't be stable. >>>> >>>> I think these warnings were added on purpose, though I also see that >>>> there are only values for these in device tree for Tegra186 and=20 >>>> Tegra194 >>>> but not Tegra210 where these should also be necessary. >> >> dt binding doc we have is common for MMC, SD and SDIO of all Tegras.=20 >> Its not mandatory to have both 3v3 and 1v8 in device tree as based on=20 >> signal mode. >> >> As these driver strengths are SoC specific, they are part of Tegra=20 >> SoC specific device tree where same values will be applicable to all=20 >> Tegra SoC specific platforms. >> >> Based on interface usage on platform, we use one or both of them like=20 >> sdcard supports dual voltage and we use both 3V3 and 1V8 but if same=20 >> interface is used for WIFI SD we use 1V8 only. >> >> So made these dt properties as optional. >> >> Other reason they are optional is, Tegra210 and prior has drive=20 >> strength settings part of apb_misc and Tegra186 and later has driver=20 >> strengths part of SDMMC controller. So, >> >> - Pinctrls "sdmmc-3v3-drv" and "sdmmc-1v8-drv" for driver strengths=20 >> are applicable for Tegra210 and prior. >> - dt properties pad-autocal-pull-up/down-offset-1v8/3v3-timeout are=20 >> for T186 onwards for driver strengths >> >> Looks like dt binding doc need fix to clearly document these based on=20 >> SoC or agree with Yaml we can conditionally specify pinctrl or dt=20 >> properties based on SoC dependent. >> >> >>>> Adding Sowjanya who wrote this code. Perhaps she can clarify why the >>>> warnings were added. If these values /should/ be there on a subset of >>>> Tegra, then I think we should keep them, or add them again, but=20 >>>> perhaps >>>> add a better way of identifying when they are necessary and when it is >>>> safe to work without them. >>>> >>>> That said, looking at those checks I wonder if they are perhaps just >>>> wrong. Or at the very least they seem redundant. It looks to me like >>>> they can just be: >>>> >>>> =C2=A0=C2=A0=C2=A0=C2=A0if (tegra_host->pinctrl_state_XYZ =3D=3D NULL)= { >>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ... >>>> =C2=A0=C2=A0=C2=A0=C2=A0} >>>> >>>> That !IS_ERR(...) doesn't seem to do anything. But in that case, it's >>>> also obvious why we're warning about them on platforms where these >>>> properties don't exist in DT. >> >> As drive strengths are through dt properties for T186 and later and=20 >> thru pinctrl for T210 and prior, driver first checks for dt autocal=20 >> timeout pull-up/down properties and if they are not found, it then=20 >> checks for presence of pinctrl_state_xyx_drv only when valid=20 >> pinctrl_state_xyz is present. >> >> Driver expects either pinctrl or dt properties and shows warning when=20 >> neither of them are present as its mandatory to use fixed driver=20 >> strengths when auto calibration fails. >> >> =C2=A0=C2=A0=C2=A0 err =3D device_property_read_u32(host->mmc->parent, >> =C2=A0=C2=A0=C2=A0 =C2=A0=C2=A0=C2=A0 =C2=A0=C2=A0=C2=A0 "nvidia,pad-aut= ocal-pull-down-offset-3v3-timeout", >> =C2=A0=C2=A0=C2=A0 =C2=A0=C2=A0=C2=A0 =C2=A0=C2=A0=C2=A0 &autocal->pull_= down_3v3_timeout); >> =C2=A0=C2=A0=C2=A0 if (err) { >> =C2=A0=C2=A0=C2=A0 =C2=A0=C2=A0=C2=A0 if (!IS_ERR(tegra_host->pinctrl_st= ate_3v3) && >> =C2=A0=C2=A0=C2=A0 =C2=A0=C2=A0=C2=A0 =C2=A0=C2=A0=C2=A0 (tegra_host->pi= nctrl_state_3v3_drv =3D=3D NULL)) >> =C2=A0=C2=A0=C2=A0 =C2=A0=C2=A0=C2=A0 =C2=A0=C2=A0=C2=A0 pr_warn("%s: Mi= ssing autocal timeout 3v3-pad drvs\n", >> =C2=A0=C2=A0=C2=A0 =C2=A0=C2=A0=C2=A0 =C2=A0=C2=A0=C2=A0 =C2=A0=C2=A0=C2= =A0 mmc_hostname(host->mmc)); >> =C2=A0=C2=A0=C2=A0 =C2=A0=C2=A0=C2=A0 autocal->pull_down_3v3_timeout =3D= 0; >> =C2=A0=C2=A0=C2=A0 } >> >>>> >>>> So I think we either need to add those values where appropriate so=20 >>>> that >>>> the warning doesn't show, or we need to narrow down where they are >>>> really needed and add a corresponding condition. >>>> >>>> But again, perhaps Sowjanya can help clarify if these really are only >>>> needed on Tegra210 and later or if these also apply to older chips. >>> Either way will be cleaner to convert the DT binding to YAML rather=20 >>> than >>> clutter the driver, IMO. >>> >> >> >> > Auto calibration is present from Tegra30 onward and looking into=20 > change where autocalibration was added to sdhci driver somehow it was=20 > enabled only for T30/T210/T186/T194. > > tegra_sdhci_parse_pad_autocal_dt() was added when auto-calibration was=20 > added to driver and I see this dt parse is being done irrespective of=20 > NVQUIRK_HAS_PADCALIB quirk so even on platforms without auto cal=20 > enabled in driver, these messages shows up. > > This should be fixed in driver to allow=20 > tegra_sdhci_parse_pad_autocal_dt() only when NVQUIRK_HAS_PADCALIB is=20 > set to avoid dt parsing to happen on platforms that don't have auto=20 > cal enabled. Warning on missing drive strengths when auto cal is enabled should be=20 present as we should switch to fixed recommended drive strengths when=20 auto cal fails. So probably proper fix should be - allow tegra_sdhci_parse_pad_autocal_dt() only when=20 NVQUIRK_HAS_PADCALIB is set - current driver sets NVQUIRK_HAS_PADCALIB for T30 as well so need to=20 add pinctrls "sdmmc-3v3-drv" and "sdmmc-1v8-drv" to Tegra30 device tree. - Keep warning message of missing auto cal timeouts as its mandatory to=20 use fixed recommended driver strengths when auto cal fails.