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Subject: Re: [PATCH 3/4] clk/soc: mediatek: mt6779: Bind clock driver from platform device To: Chun-Kuang Hu , matthias.bgg@kernel.org Cc: Rob Herring , Matthias Brugger , Michael Turquette , Stephen Boyd , Kate Stewart , devicetree@vger.kernel.org, Greg Kroah-Hartman , linux-kernel , "moderated list:ARM/Mediatek SoC support" , Linux ARM , mtk01761 , Thomas Gleixner , linux-clk@vger.kernel.org, Allison Randal References: <20200518113156.25009-1-matthias.bgg@kernel.org> <20200518113156.25009-3-matthias.bgg@kernel.org> From: Matthias Brugger Autocrypt: addr=mbrugger@suse.com; prefer-encrypt=mutual; keydata= mQINBFP1zgUBEAC21D6hk7//0kOmsUrE3eZ55kjc9DmFPKIz6l4NggqwQjBNRHIMh04BbCMY fL3eT7ZsYV5nur7zctmJ+vbszoOASXUpfq8M+S5hU2w7sBaVk5rpH9yW8CUWz2+ZpQXPJcFa OhLZuSKB1F5JcvLbETRjNzNU7B3TdS2+zkgQQdEyt7Ij2HXGLJ2w+yG2GuR9/iyCJRf10Okq gTh//XESJZ8S6KlOWbLXRE+yfkKDXQx2Jr1XuVvM3zPqH5FMg8reRVFsQ+vI0b+OlyekT/Xe 0Hwvqkev95GG6x7yseJwI+2ydDH6M5O7fPKFW5mzAdDE2g/K9B4e2tYK6/rA7Fq4cqiAw1+u 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UHUEIsTwPWs2Q87k7vjYyrcyAOarX2X5pvMQvpAMADGf2Z3wrCsDdG25w2HztweUNd9QEprt JG8GNNzMOD4cQ82Ta7eGvPWPeXauWJDLVR9jHtWT9Ot3BQgmApLxACvwvD1a69jaFKov28SP HxUCQ9Y1Y/Ct Message-ID: <3a8b3846-c399-2193-a203-8707d693dad8@suse.com> Date: Tue, 19 May 2020 23:26:34 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.7.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 19/05/2020 17:10, Chun-Kuang Hu wrote: > Hi, Matthias: > > 於 2020年5月18日 週一 下午7:33寫道: >> >> From: Matthias Brugger >> >> The mmsys driver is now the top level entry point for the multimedia >> system (mmsys), we bind the clock driver by creating a platform device. >> We also bind the MediaTek DRM driver which is not yet implement and >> therefor will errror out for now. >> >> Signed-off-by: Matthias Brugger >> --- >> >> drivers/clk/mediatek/clk-mt6779-mm.c | 9 ++------- >> drivers/soc/mediatek/mtk-mmsys.c | 8 ++++++++ >> 2 files changed, 10 insertions(+), 7 deletions(-) >> >> diff --git a/drivers/clk/mediatek/clk-mt6779-mm.c b/drivers/clk/mediatek/clk-mt6779-mm.c >> index fb5fbb8e3e41..059c1a41ac7a 100644 >> --- a/drivers/clk/mediatek/clk-mt6779-mm.c >> +++ b/drivers/clk/mediatek/clk-mt6779-mm.c >> @@ -84,15 +84,11 @@ static const struct mtk_gate mm_clks[] = { >> GATE_MM1(CLK_MM_DISP_OVL_FBDC, "mm_disp_ovl_fbdc", "mm_sel", 16), >> }; >> >> -static const struct of_device_id of_match_clk_mt6779_mm[] = { >> - { .compatible = "mediatek,mt6779-mmsys", }, >> - {} >> -}; >> - >> static int clk_mt6779_mm_probe(struct platform_device *pdev) >> { >> + struct device *dev = &pdev->dev; >> + struct device_node *node = dev->parent->of_node; >> struct clk_onecell_data *clk_data; >> - struct device_node *node = pdev->dev.of_node; >> >> clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK); >> >> @@ -106,7 +102,6 @@ static struct platform_driver clk_mt6779_mm_drv = { >> .probe = clk_mt6779_mm_probe, >> .driver = { >> .name = "clk-mt6779-mm", >> - .of_match_table = of_match_clk_mt6779_mm, >> }, >> }; >> >> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c >> index fee64c8d3020..dc15808cf3a3 100644 >> --- a/drivers/soc/mediatek/mtk-mmsys.c >> +++ b/drivers/soc/mediatek/mtk-mmsys.c >> @@ -88,6 +88,10 @@ static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { >> .clk_driver = "clk-mt2712-mm", >> }; >> >> +static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = { >> + .clk_driver = "clk-mt6779-mm", > > This patch looks good to me, but I've one question: why drm driver > just use single "mediatek-drm" for sub driver name, but clock driver > has different name for each SoC? > Could we just use single name for clock driver such as "mediatek-clk-mm"? Because the DRM for all SoCs are handled in the same driver, while we have a different clock drivers for each SoC. So we need to specify which clock driver we want to load. If we want to change that, we would need to refactor heavily the clock drivers for all MediaTek SoCs. I don't think it's worth the effort. Regards, Matthias > > Regards, > Chun-Kuang. > >> +}; >> + >> static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = { >> .clk_driver = "clk-mt6797-mm", >> }; >> @@ -343,6 +347,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = { >> .compatible = "mediatek,mt2712-mmsys", >> .data = &mt2712_mmsys_driver_data, >> }, >> + { >> + .compatible = "mediatek,mt6779-mmsys", >> + .data = &mt6779_mmsys_driver_data, >> + }, >> { >> .compatible = "mediatek,mt6797-mmsys", >> .data = &mt6797_mmsys_driver_data, >> -- >> 2.26.2 >> >> >> _______________________________________________ >> Linux-mediatek mailing list >> Linux-mediatek@lists.infradead.org >> http://lists.infradead.org/mailman/listinfo/linux-mediatek