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[23.128.96.18]) by mx.google.com with ESMTP id dr12si1381734ejc.352.2020.05.19.20.34.00; Tue, 19 May 2020 20:34:23 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b="Txe/8vd3"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728613AbgETDcC (ORCPT + 99 others); Tue, 19 May 2020 23:32:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38250 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726432AbgETDcB (ORCPT ); Tue, 19 May 2020 23:32:01 -0400 Received: from mail-ot1-x343.google.com (mail-ot1-x343.google.com [IPv6:2607:f8b0:4864:20::343]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9BC7DC061A0E for ; Tue, 19 May 2020 20:32:01 -0700 (PDT) Received: by mail-ot1-x343.google.com with SMTP id o13so1382979otl.5 for ; Tue, 19 May 2020 20:32:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=E2vK9F/eA14thO30W50mK/uC9vmImhp6JcvtaBfalus=; b=Txe/8vd30AxuY9Cp9qMRIiPjVlgPWo9BHR/CL3Wgqy6AE7SyYWidotTjxY0/jDStqh Ixc+8EiaFrLUnoBWEHJctLDH3m2qq2KwDbsdtadTMfx8EJueY6SL2X56MtvhsbDsQygO 6q1W7v95tPKwj9Eev816CGRFvjir6CPE2KBugcO5cOJW04maMQuakYqFLoZFLY1LmDF/ FoPvJZTz23UQT8nTIKEIoQ+iA5H5ibQx15P4TJmxhdMn20D6ir8WmVscb8VWNl/4z1WK YreGTJSkEOkBfXnxGJ3pH4P4WBre0cPzeQ+MoI2jsi8a/LX7Ie/gSCRdY8R2gadala6/ i+Xg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=E2vK9F/eA14thO30W50mK/uC9vmImhp6JcvtaBfalus=; b=pZo9L0AfYnAhrbYPsSvCHem2FpwlgZTkNq/gA5xVp2EXmZGseH8/yzIKh12H6Sm1Rb 42yRDfSEhT95SI4sSAh1LoeuHb/BlcY9pBDDumJzIDP1Hmr05Q9RZ7YAQ+yCzhmJTgY3 RUuYKoiL4uzVPf6LmavvKgnAl4vwDt37c46r10r9k1HdBxz/Rh4cn+KSQ3fM4dgRLcZ5 4Pqubl1O3u/hxJ2EWlOMH8fxThODas082mcoT6kG9lLIJKJboxqS5kHkILqBrdAvtjFK NUby4PS4tt77RU48udWKyjXWCDGwW/Mdir571+mMO2Mau6HXwVY+ftN9xxIqJMxZI106 JWGg== X-Gm-Message-State: AOAM530Ps+Sjtp8jCo9/zJzo1qN9upPDqXyxLN2jhbKKb0ZJd7wG3JLb yk1jcPCPn/zokGeVSUqoES4GDXy9N9GVrj2bjTaYjP+4 X-Received: by 2002:a9d:32b4:: with SMTP id u49mr1768191otb.304.1589945521027; Tue, 19 May 2020 20:32:01 -0700 (PDT) MIME-Version: 1.0 References: <1588151843-2133-1-git-send-email-peng.fan@nxp.com> <20200520005638.GA11739@dragon> In-Reply-To: <20200520005638.GA11739@dragon> From: Shawn Guo Date: Wed, 20 May 2020 11:31:50 +0800 Message-ID: Subject: Re: [PATCH V2 0/3] ARM: imx: move cpu code to drivers/soc/imx To: peng.fan@nxp.com Cc: linux-arm-kernel@lists.infradead.org, abel.vesa@nxp.com, Anson Huang , ard.biesheuvel@linaro.org, Fabio Estevam , Sascha Hauer , Linux Kernel Mailing List , NXP Linux Team , Sascha Hauer , git@andred.net, leonard.crestez@nxp.com, info@metux.net, allison@lohutok.net Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, May 20, 2020 at 8:57 AM Shawn Guo wrote: > > On Wed, Apr 29, 2020 at 05:17:20PM +0800, peng.fan@nxp.com wrote: > > From: Peng Fan > > > > V2: > > Keep i.MX1/2/3/5 cpu type for completness > > Correct return value in patch 1/3 > > use CONFIG_ARM to guard compile soc-imx.c in patch 3/3 > > > > V1: > > https://patchwork.kernel.org/cover/11433689/ > > RFC version : > > https://patchwork.kernel.org/cover/11336433/ > > > > Nothing changed in v1, just rename to formal patches > > > > Shawn, > > The original concern has been eliminated in RFC discussion, > > so this patchset is ready to be in next. > > Thanks. > > > > Follow i.MX8, move the soc device register code to drivers/soc/imx > > to simplify arch/arm/mach-imx/cpu.c > > > > I planned to use similar logic as soc-imx8m.c to restructure soc-imx.c > > and merged the two files into one. But not sure, so still keep > > the logic in cpu.c. > > > > There is one change is the platform devices are not under > > /sys/devices/soc0 after patch 1/4. Actually ARM64 platform > > devices are not under /sys/devices/soc0, such as i.MX8/8M. > > So it should not hurt to let the platform devices under platform dir. > > > > Peng Fan (3): > > ARM: imx: use device_initcall for imx_soc_device_init > > ARM: imx: move cpu definitions into a header > > soc: imx: move cpu code to drivers/soc/imx > > Applied all, thanks. Unfortunately, I have to drop this, as it turns out the series needs a rebase onto for-next. The series conflicts with 'ARM: vf610: report soc info via soc device' there. Shawn