Received: by 2002:a25:868d:0:0:0:0:0 with SMTP id z13csp439701ybk; Wed, 20 May 2020 03:35:03 -0700 (PDT) X-Google-Smtp-Source: ABdhPJydJVQYeq9c9FWm0W12HOVgVoLN0kWnH13zJJJgBq1Pf/oNhGmpuEymFbpHEHB1HSWkChhn X-Received: by 2002:a50:eb0a:: with SMTP id y10mr2775835edp.312.1589970903081; Wed, 20 May 2020 03:35:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1589970903; cv=none; d=google.com; s=arc-20160816; b=eVeUX7GFtrhEqM4wB2+kwOpNFOsJ3LsgN94E4d9yfaLFy7VW4TWP2ORT89h+8k1yUD 3tVvwQI1KfwChPQSc/Z+OvgatW0SVvCM7pnvEZU/X/CsZ3MI6DxfjY+sksxANL2XvVL1 VQBK+F6LpFKhYhP/octfPoHCTr70srcFHXhEgfFBxfdsN9tP+XBwSekjtEapkAfUOl2C YKqSrcibH4EwS4oQ8xD1wlb03HYaE8YsphYUZo8421uXiHNsMkJQuHN62qcDdk/W03BK KM3YKwbkGuNLMo3wYJt8APUalxcuuvzMxEXwY3rhCn7DizK7yneaJ9bas/hVEHfAEUlX SpAg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-language :content-transfer-encoding:in-reply-to:mime-version:user-agent:date :message-id:references:cc:to:from:subject; bh=vgtQ+227IPqWzEVTXveRheHmsdgKM2kSX5sE3Bq87Q0=; b=At2nhX8zbA2mioj3EAtiz48XOcmN4uKRJr+u07d9/9NrrPr23A4nXAT8aoFWQ6uQ3o t4u2Z8CL4hNiLtXGlzdjTv7bxfHWduBrjuUglntJ+/ETfPu4syHy2R0GjhxT2Jjrgqix Q0SIJWadLJOfC360+b8QoOZI3weKXMbvwYYIrBjNC1sZuMiW2tExuZ7r/tIJPuBDsloj IxJXWsH6RsVYrcH4D0Duf9Az+Ejm8ngFxVRovX5AF4FDNt35D8o0gF5rCwnvsVW3Io4o ACmlEk0OeiURBfVU2nYEVCnLGH7FCj5VOw7PFTT96LTnz3NeA4ZGHbui+3TfrNimuDCM maEg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id mc5si1553577ejb.6.2020.05.20.03.34.39; Wed, 20 May 2020 03:35:03 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726838AbgETKaU (ORCPT + 99 others); Wed, 20 May 2020 06:30:20 -0400 Received: from foss.arm.com ([217.140.110.172]:52538 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726837AbgETKaR (ORCPT ); Wed, 20 May 2020 06:30:17 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9347655D; Wed, 20 May 2020 03:30:16 -0700 (PDT) Received: from [10.37.8.79] (unknown [10.37.8.79]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B658C3F68F; Wed, 20 May 2020 03:30:13 -0700 (PDT) Subject: Re: [PATCH 0/3] arm64: perf: Add support for Perf NMI interrupts From: Alexandru Elisei To: Mark Rutland , Lecopzer Chen Cc: Sumit Garg , Jian-Lin Chen , Will Deacon , alexander.shishkin@linux.intel.com, Catalin Marinas , yj.chiang@mediatek.com, Linux Kernel Mailing List , acme@kernel.org, Peter Zijlstra , mingo@redhat.com, linux-mediatek@lists.infradead.org, linux-arm-kernel , matthias.bgg@gmail.com, namhyung@kernel.org, jolsa@redhat.com, julien.thierry.kdev@gmail.com References: <20200516124857.75004-1-lecopzer@gmail.com> <20200518104524.GA1224@C02TD0UTHF1T.local> Message-ID: <8a1022c0-da2b-c83d-81cd-44b11149496b@arm.com> Date: Wed, 20 May 2020 11:30:45 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.8.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Content-Language: en-US Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On 5/18/20 12:17 PM, Alexandru Elisei wrote: > Hi, > > On 5/18/20 11:45 AM, Mark Rutland wrote: >> Hi all, >> >> On Mon, May 18, 2020 at 02:26:00PM +0800, Lecopzer Chen wrote: >>> HI Sumit, >>> >>> Thanks for your information. >>> >>> I've already implemented IPI (same as you did [1], little difference >>> in detail), hardlockup detector and perf in last year(2019) for >>> debuggability. >>> And now we tend to upstream to reduce kernel maintaining effort. >>> I'm glad if someone in ARM can do this work :) >>> >>> Hi Julien, >>> >>> Does any Arm maintainers can proceed this action? >> Alexandru (Cc'd) has been rebasing and reworking Julien's patches, which >> is my preferred approach. >> >> I understand that's not quite ready for posting since he's investigating >> some of the nastier subtleties (e.g. mutual exclusion with the NMI), but >> maybe we can put the work-in-progress patches somewhere in the mean >> time. >> >> Alexandru, do you have an idea of what needs to be done, and/or when you >> expect you could post that? > I'm currently working on rebasing the patches on top of 5.7-rc5, when I have > something usable I'll post a link (should be a couple of days). After that I will > address the review comments, and I plan to do a thorough testing because I'm not > 100% confident that some of the assumptions around the locks that were removed are > correct. My guess is this will take a few weeks. Pushed a WIP branch on linux-arm.org [1]: git clone -b WIP-pmu-nmi git://linux-arm.org/linux-ae Practically untested, I only did perf record on a defconfig kernel running on the model. [1] http://www.linux-arm.org/git?p=linux-ae.git;a=shortlog;h=refs/heads/WIP-pmu-nmi Thanks, Alex > > Thanks, > Alex >> Thanks, >> Mark. >> >>> This is really useful in debugging. >>> Thank you!! >>> >>> >>> >>> [1] https://lkml.org/lkml/2020/4/24/328 >>> >>> >>> Lecopzer >>> >>> Sumit Garg 於 2020年5月18日 週一 下午1:46寫道: >>>> + Julien >>>> >>>> Hi Lecopzer, >>>> >>>> On Sat, 16 May 2020 at 18:20, Lecopzer Chen wrote: >>>>> These series implement Perf NMI funxtionality and depends on >>>>> Pseudo NMI [1] which has been upstreamed. >>>>> >>>>> In arm64 with GICv3, Pseudo NMI was implemented for NMI-like interruts. >>>>> That can be extended to Perf NMI which is the prerequisite for hard-lockup >>>>> detector which had already a standard interface inside Linux. >>>>> >>>>> Thus the first step we need to implement perf NMI interface and make sure >>>>> it works fine. >>>>> >>>> This is something that is already implemented via Julien's patch-set >>>> [1]. Its v4 has been floating since July, 2019 and I couldn't find any >>>> major blocking comments but not sure why things haven't progressed >>>> further. >>>> >>>> Maybe Julien or Arm maintainers can provide updates on existing >>>> patch-set [1] and how we should proceed further with this interesting >>>> feature. >>>> >>>> And regarding hard-lockup detection, I have been able to enable it >>>> based on perf NMI events using Julien's perf patch-set [1]. Have a >>>> look at the patch here [2]. >>>> >>>> [1] https://patchwork.kernel.org/cover/11047407/ >>>> [2] http://lists.infradead.org/pipermail/linux-arm-kernel/2020-May/732227.html >>>> >>>> -Sumit >>>> >>>>> Perf NMI has been test by dd if=/dev/urandom of=/dev/null like the link [2] >>>>> did. >>>>> >>>>> [1] https://lkml.org/lkml/2019/1/31/535 >>>>> [2] https://www.linaro.org/blog/debugging-arm-kernels-using-nmifiq >>>>> >>>>> >>>>> Lecopzer Chen (3): >>>>> arm_pmu: Add support for perf NMI interrupts registration >>>>> arm64: perf: Support NMI context for perf event ISR >>>>> arm64: Kconfig: Add support for the Perf NMI >>>>> >>>>> arch/arm64/Kconfig | 10 +++++++ >>>>> arch/arm64/kernel/perf_event.c | 36 ++++++++++++++++++------ >>>>> drivers/perf/arm_pmu.c | 51 ++++++++++++++++++++++++++++++---- >>>>> include/linux/perf/arm_pmu.h | 6 ++++ >>>>> 4 files changed, 88 insertions(+), 15 deletions(-) >>>>> >>>>> -- >>>>> 2.25.1 >>>>> >>>>> >>>>> _______________________________________________ >>>>> linux-arm-kernel mailing list >>>>> linux-arm-kernel@lists.infradead.org >>>>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel