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Date:   Wed, 20 May 2020 19:51:38 +0800
From:   Jiaxun Yang <jiaxun.yang@flygoat.com>
To:     Thomas Gleixner <tglx@linutronix.de>, maz@kernel.org
CC:     Jason Cooper <jason@lakedaemon.net>,
        Rob Herring <robh+dt@kernel.org>,
        Huacai Chen <chenhc@lemote.com>, linux-kernel@vger.kernel.org,
        devicetree@vger.kernel.org, linux-mips@vger.kernel.org
Subject: Re: [PATCH v2 5/6] irqchip: Add Loongson PCH MSI controller
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References: <20200422142428.1249684-1-jiaxun.yang@flygoat.com> <20200428063247.2223499-1-jiaxun.yang@flygoat.com> <20200428063247.2223499-5-jiaxun.yang@flygoat.com> <874ksk3uda.fsf@nanos.tec.linutronix.de> <871rno3uab.fsf@nanos.tec.linutronix.de>
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=E4=BA=8E 2020=E5=B9=B45=E6=9C=8813=E6=97=A5 GMT+08:00 =E4=B8=8B=E5=8D=888=
:15:40, Thomas Gleixner <tglx@linutronix=2Ede> =E5=86=99=E5=88=B0:
>Thomas Gleixner <tglx@linutronix=2Ede> writes:
>> Jiaxun Yang <jiaxun=2Eyang@flygoat=2Ecom> writes:
>>> +
>>> +struct pch_msi_data {
>>> +	spinlock_t		msi_map_lock;
>>> +	phys_addr_t		doorbell;
>>> +	u32			irq_first;	/* The vector number that MSIs starts */
>>> +	u32			num_irqs;	/* The number of vectors for MSIs */
>>> +	unsigned long		*msi_map;
>>> +};
>>> +
>>> +static void pch_msi_mask_msi_irq(struct irq_data *d)
>>> +{
>>> +	pci_msi_mask_irq(d);
>>> +	irq_chip_mask_parent(d);
>>> +}
>>> +
>>> +static void pch_msi_unmask_msi_irq(struct irq_data *d)
>>> +{
>>> +	pci_msi_unmask_irq(d);
>>> +	irq_chip_unmask_parent(d);
>>
>> The ordering of mask and unmask is assymetric=2E That does not make sen=
se=2E
>>
>>> +static struct msi_domain_info pch_msi_domain_info =3D {
>>> +	=2Eflags		=3D MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
>>> +			  MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX,
>>> +	=2Echip	=3D &pch_msi_irq_chip,
>>
>> Please maintain tabular layout=2E
>
>Ooops=2E Wanted to reply to V3, but the comments are valid for V3 as well=
=2E

All fixed in v4=2E

Please review=2E

Thanks!


>
>Thanks,
>
>        tglx

--=20
Jiaxun Yang