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Message-ID: <347f6b51e6ab74ad2ccf1dd60a345ce41b0defb3.camel@suse.de>
Subject: Re: [PATCH 04/15] PCI: brcmstb: Add compatibily of other chips
From:   Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
To:     Jim Quinlan <james.quinlan@broadcom.com>
Cc:     Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
        Rob Herring <robh@kernel.org>,
        Bjorn Helgaas <bhelgaas@google.com>,
        Florian Fainelli <f.fainelli@gmail.com>,
        "maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE" 
        <bcm-kernel-feedback-list@broadcom.com>,
        "moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE" 
        <linux-rpi-kernel@lists.infradead.org>,
        "moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE" 
        <linux-arm-kernel@lists.infradead.org>,
        "open list:PCI NATIVE HOST BRIDGE AND ENDPOINT DRIVERS" 
        <linux-pci@vger.kernel.org>,
        open list <linux-kernel@vger.kernel.org>
Date:   Wed, 20 May 2020 16:41:31 +0200
In-Reply-To: <CA+-6iNwE7CkD0r7Z0cKGXxE14Unf7ZGsr4q7Z8dPhgYYXHXHEg@mail.gmail.com>
References: <20200519203419.12369-1-james.quinlan@broadcom.com>
         <20200519203419.12369-5-james.quinlan@broadcom.com>
         <5a52e39ce99214877e83104b8ea9f95c0d5b4e90.camel@suse.de>
         <CA+-6iNwE7CkD0r7Z0cKGXxE14Unf7ZGsr4q7Z8dPhgYYXHXHEg@mail.gmail.com>
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On Wed, 2020-05-20 at 10:30 -0400, Jim Quinlan wrote:
> On Wed, May 20, 2020 at 7:51 AM Nicolas Saenz Julienne
> <nsaenzjulienne@suse.de> wrote:
[...]
> > > +
> > > +static const struct pcie_cfg_data bcm7278_cfg =3D {
> > > +     .reg_field_info =3D pcie_reg_field_info_bcm7278,
> > > +     .offsets        =3D pcie_offset_bcm7278,
> > > +     .type           =3D BCM7278,
> > > +};
> >=20
> > It's not essential, but if v2 is due I'd suggest factoring out the bcm2=
728
> > specific structures above, and moving them to patch #15. This will keep=
 a
> > clearer division between the patch introducing the infrastructure and t=
he
> > one
> > adding the support for a new device.
> The problem is that one of the commits needs the 7278 type so it has
> to be declared earlier.

Fair enough.

> > > +
> > >  struct brcm_msi {
> > >       struct device           *dev;
> > >       void __iomem            *base;
> > > @@ -176,6 +238,9 @@ struct brcm_pcie {
> > >       int                     gen;
> > >       u64                     msi_target_addr;
> > >       struct brcm_msi         *msi;
> > > +     const int               *reg_offsets;
> > > +     const int               *reg_field_info;
> > > +     enum pcie_type          type;
> > >  };
> > >=20
> > >  /*
> > > @@ -602,20 +667,21 @@ static struct pci_ops brcm_pcie_ops =3D {
> > >=20
> > >  static inline void brcm_pcie_bridge_sw_init_set(struct brcm_pcie *pc=
ie,
> > > u32
> > > val)
> > >  {
> > > -     u32 tmp;
> > > +     u32 tmp, mask =3D  pcie->reg_field_info[RGR1_SW_INIT_1_INIT_MAS=
K];
> > > +     u32 shift =3D pcie->reg_field_info[RGR1_SW_INIT_1_INIT_SHIFT];
> >=20
> > I don't think you need shift here, IIUC u32p_replace_bits() will take c=
are
> > of
> > all the masking and shifting internally, moreover, you'd be able to dro=
p the
> > shift entry from reg_field_info.
> Got it.
> > > -     tmp =3D readl(pcie->base + PCIE_RGR1_SW_INIT_1);
> > > -     u32p_replace_bits(&tmp, val, PCIE_RGR1_SW_INIT_1_INIT_MASK);
> > > -     writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1);
> > > +     tmp =3D readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
> > > +     tmp =3D (tmp & ~mask) | ((val << shift) & mask);
> > > +     writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
> > >  }
> >=20
> > Regards,
> > Nicolas
> >=20
> Thanks!
> Jim


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