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From:   Maxim Levitsky <mlevitsk@redhat.com>
To:     kvm@vger.kernel.org
Cc:     linux-kernel@vger.kernel.org, Maxim Levitsky <mlevitsk@redhat.com>
Subject: [PATCH 0/2] Fix breakage from adding MSR_IA32_UMWAIT_CONTROL
Date:   Wed, 20 May 2020 19:07:38 +0300
Message-Id: <20200520160740.6144-1-mlevitsk@redhat.com>
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Currently code in kvm_get_supported_msrs always=0D
returns this msr as supported by KVM, however it=0D
is not supported at all on AMD and it is only supported=0D
on few select Intel systems.=0D
=0D
This happened to work in native virtualization case,=0D
because KVM's code also tries to read these msrs,=0D
and on an exception drops them from the supported msr list.=0D
=0D
However when running nested, and outer hypervisor set=0D
to ignore unknown msrs, the read from this msr doesn't get=0D
an excption, and thus KVM thinks that this msr should be on=0D
supported msr list.=0D
=0D
I don't think we should rely on exception to check if a feature=0D
is supported since that msr can be even in theory assigned to something=0D
else on AMD for example.=0D
=0D
Also I included a cosmetic fix for an issue I found in the same function.=0D
=0D
Best regards,=0D
	Maxim Levitsky=0D
=0D
Maxim Levitsky (2):=0D
  kvm: cosmetic: remove wrong braces in kvm_init_msr_list switch=0D
  kvm/x86: don't expose MSR_IA32_UMWAIT_CONTROL unconditionally=0D
=0D
 arch/x86/kvm/x86.c | 7 +++++--=0D
 1 file changed, 5 insertions(+), 2 deletions(-)=0D
=0D
-- =0D
2.26.2=0D
=0D