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Thu, 21 May 2020 13:34:10 +0000 From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Albert Ou , Daniel Lezcano , Thomas Gleixner , Jason Cooper , Marc Zyngier Cc: Atish Patra , Alistair Francis , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v5 6/6] RISC-V: Force select RISCV_INTC for CONFIG_RISCV Date: Thu, 21 May 2020 19:03:01 +0530 Message-Id: <20200521133301.816665-7-anup.patel@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200521133301.816665-1-anup.patel@wdc.com> References: <20200521133301.816665-1-anup.patel@wdc.com> Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: MA1PR0101CA0033.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:22::19) To DM6PR04MB6201.namprd04.prod.outlook.com (2603:10b6:5:127::32) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from wdc.com (106.51.30.72) by MA1PR0101CA0033.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:22::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3021.23 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: sGwvgAS7gAjP62nv4FIF5IatnTA0rvUSOXCeDY4HT8a+FbLZJiDDcivGmN8HqEVsm67Fb1LP5Eu4ke1jRXUOoqKxJfp107nL51mAhj6rvXGsgqPERLCWKmQb3bMKT6GI3Z+6kDK9DJ2tpUQ4FPlEUji09vOXv1kWmffN9gE89zZ0SQ9b5iPYoYXaC/pleFDvf0dV+kK3tqXyFdnKrw8QKCLinOjJ9DZc+G/3spqpI4MRLQJ+/eAZ6KsrcN9FXrC/2BWN9Kuu6W4iqxUbh33nGS57Sbkl5zcvIe1jE/CPjxC6Q1nIvHMQXT0+GEkRzT0K6mSeOY9g2p4svoaIudfSJC78bwEgvjiftORG7MmxP0M0vcUY7z5vcO8Om/LB2lp1RdvZ1FcwmHysMSEdAu20eWeWY5aEZGBDmuk4PVC691/Rix6L3xwh312mTW2unbVOf8LZU61laOj+c2fIONMVQYKpZLTrH/DyoqqjkJNg2GA= X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: 6b7e5965-f81c-4bc5-40c3-08d7fd8ba45a X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 May 2020 13:34:10.0751 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: v4fhoZJ0fMhOfhgMp5Ak8Xs73pz3WTG5r8CY2KccCY4Eowli6fkkSzd9j2MzznUNE9/JMTaAbUIC+1OajnXVcA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR04MB5292 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The RISC-V per-HART local interrupt controller driver is mandatory for all RISC-V system (with/without MMU) hence we force select it for CONFIG_RISCV (just like RISCV_TIMER). Signed-off-by: Anup Patel --- arch/riscv/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 822cb0e1a380..2cf0c83c1a47 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -51,6 +51,7 @@ config RISCV select THREAD_INFO_IN_TASK select PCI_DOMAINS_GENERIC if PCI select PCI_MSI if PCI + select RISCV_INTC select RISCV_TIMER select GENERIC_IRQ_MULTI_HANDLER select GENERIC_ARCH_TOPOLOGY if SMP -- 2.25.1