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[76.210.143.223]) by smtp.gmail.com with ESMTPSA id mu17sm5941296pjb.53.2020.05.21.15.06.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 May 2020 15:06:18 -0700 (PDT) Date: Thu, 21 May 2020 15:06:18 -0700 (PDT) X-Google-Original-Date: Thu, 21 May 2020 15:00:02 PDT (-0700) Subject: Re: [PATCH v2 3/3] irqchip/sifive-plic: Improve boot prints for multiple PLIC instances In-Reply-To: <20200518091441.94843-4-anup.patel@wdc.com> CC: Paul Walmsley , tglx@linutronix.de, jason@lakedaemon.net, Marc Zyngier , Atish Patra , Alistair Francis , anup@brainfault.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel From: Palmer Dabbelt To: Anup Patel Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 18 May 2020 02:14:41 PDT (-0700), Anup Patel wrote: > We improve PLIC banner to help distinguish multiple PLIC instances > in boot time prints. > > Signed-off-by: Anup Patel > --- > drivers/irqchip/irq-sifive-plic.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c > index 6c54abf5cc5e..d9c53f85a68e 100644 > --- a/drivers/irqchip/irq-sifive-plic.c > +++ b/drivers/irqchip/irq-sifive-plic.c > @@ -380,8 +380,8 @@ static int __init plic_init(struct device_node *node, > plic_cpuhp_setup_done = true; > } > > - pr_info("mapped %d interrupts with %d handlers for %d contexts.\n", > - nr_irqs, nr_handlers, nr_contexts); > + pr_info("%pOFP: mapped %d interrupts with %d handlers for" > + " %d contexts.\n", node, nr_irqs, nr_handlers, nr_contexts); > set_handle_irq(plic_handle_irq); > return 0; Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt