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[209.85.222.169]) by smtp.gmail.com with ESMTPSA id m7sm6624847qti.6.2020.05.21.22.23.27 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 21 May 2020 22:23:28 -0700 (PDT) Received: by mail-qk1-f169.google.com with SMTP id m11so9689569qka.4; Thu, 21 May 2020 22:23:27 -0700 (PDT) X-Received: by 2002:a05:620a:6da:: with SMTP id 26mr13060082qky.196.1590125007554; Thu, 21 May 2020 22:23:27 -0700 (PDT) MIME-Version: 1.0 References: <20200520135708.GA1086370@bjorn-Precision-5520> In-Reply-To: From: Paul Burton Date: Thu, 21 May 2020 22:23:14 -0700 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: piix4-poweroff.c I/O BAR usage To: "Maciej W. Rozycki" , Bjorn Helgaas Cc: Krzysztof Wilczynski , linux-pci@vger.kernel.org, Linux Kernel Mailing List , "Maciej W. Rozycki" Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hello, On Thu, May 21, 2020 at 6:04 PM Maciej W. Rozycki wrote: > Paul may or may not be reachable anymore, so I'll step in. I'm reachable but lacking free time & with no access to Malta hardware I can't claim to be too useful here, so thanks for responding :) Before being moved to a driver (which was mostly driven by a desire to migrate Malta to a multi-platform/generic kernel using DT) this code was part of arch/mips/mti-malta/ where I added it in commit b6911bba598f ("MIPS: Malta: add suspend state entry code"). My main motivation at the time was to make QEMU exit after running poweroff, but I did ensure it worked on real Malta boards too (at least Malta-R with CoreFPGA6). Over the years since then it shocked a couple of hardware people to see software power off a Malta - if the original hardware designers had intended that to work then the knowledge had been lost over time :) I suspect the code was based on visws_machine_power_off(): https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/x86/platform/visws/visws_quirks.c?h=v3.10#n125 > > pci_request_region() takes a BAR number (0-5), but here we're passing > > PCI_BRIDGE_RESOURCES (13 if CONFIG_PCI_IOV, or 7 otherwise), which is > > the bridge I/O window. > > > > I don't think this device ([8086:7113]) is a bridge, so that resource > > should be empty. > > Hmm, isn't the resource actually set up by `quirk_piix4_acpi' though? I agree that the region used is meant to match that set up by quirk_piix4_acpi(), which also refers to it using the PCI_BRIDGE_RESOURCES macro. Thanks, Paul